AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

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ID 683064
Date 10/21/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Intel® Quartus® Prime Software SEU FIT Reports 3. Intel® Arria® 10 Error Detection and Correction Feature Architecture 4. Guidelines for Error Detection CRC and Error Correction Feature 5. Guidelines for Embedded Memory ECC Feature 6. Intel® Arria® 10 EDCRC Reference Design 7. Implementing ECC Feature in Intel® Arria® 10 ROM Design 8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 9. Document Revision History for AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices
2. Intel® Quartus® Prime Software SEU FIT Reports x
2.1. Enabling the Projected SEU FIT by Component Usage Report 2.2. SEU FIT Parameters Report 2.3. Projected SEU FIT by Component Usage Report
2.3. Projected SEU FIT by Component Usage Report x
2.3.1. Component FIT Rates 2.3.2. Raw FIT 2.3.3. Utilized FIT 2.3.4. Mitigated FIT 2.3.5. Architectural Vulnerability Factor
2.3.3. Utilized FIT x
2.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 2.3.3.2. Considerations for Small Designs
3. Intel® Arria® 10 Error Detection and Correction Feature Architecture x
3.1. Error Detection and Correction for CRAM 3.2. Memory Blocks Error Correction Code Support
3.1. Error Detection and Correction for CRAM x
3.1.1. Error Detection Cyclic Redundancy Check 3.1.2. Recovering from CRC Errors
3.1.1. Error Detection Cyclic Redundancy Check x
3.1.1.1. Column-Based and Frame-Based Check-Bits 3.1.1.2. Error Message Register
4. Guidelines for Error Detection CRC and Error Correction Feature x
4.1. Error Detection 4.2. Enabling Error Correction (Internal Scrubbing) 4.3. Interpreting CRC_ERROR
4.1. Error Detection x
4.1.1. Enabling Error Detection 4.1.2. Reading EMR
4.1.1. Enabling Error Detection x
4.1.1.1. Enabling the Error Detection CRC_ERROR Pin
4.1.2. Reading EMR x
4.1.2.1. Reading EMR using EMR Unloader IP Core 4.1.2.2. Reading EMR using HPS 4.1.2.3. Reading EMR using JTAG Interface
4.3. Interpreting CRC_ERROR x
4.3.1. CRC_ERROR Pin Behavior 4.3.2. Correctable and Uncorrectable Error
6. Intel® Arria® 10 EDCRC Reference Design x
6.1. System Requirements 6.2. Creating Intel® Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys 6.3. Design Testing with Fault Injection Debugger
6.2. Creating Intel® Arria® 10 SEU Fault Injection and Hierarchy Tagging Design with Qsys x
6.2.1. Starting Intel® Quartus® Prime Software and Opening the Reference Design Project 6.2.2. Creating New Qsys System 6.2.3. Generating Qsys System 6.2.4. Integrating Qsys System into Quartus Prime Project
6.2.2. Creating New Qsys System x
6.2.2.1. Specifying Target FPGA and Clock Settings 6.2.2.2. Adding Altera IOPLL IP Core 6.2.2.3. Adding EMR Unloader IP Core 6.2.2.4. Adding Advance SEU Detection IP Core 6.2.2.5. Adding Fault Injection IP Core 6.2.2.6. Adding Avalon-ST Splitter 6.2.2.7. Adding Serial Flash Controller
6.2.4. Integrating Qsys System into Quartus Prime Project x
6.2.4.1. Generating In-System Source and Probe IP Core 6.2.4.2. Quartus Prime Project Settings 6.2.4.3. Assigning ASD Regions 6.2.4.4. Assigning FPGA Pin Location 6.2.4.5. Compiling the Project
6.3. Design Testing with Fault Injection Debugger x
6.3.1. Converting .sof File and .smh File to .jic File 6.3.2. Programing .jic File into EPCQ-L 6.3.3. Launching Signal Tap Logic Analyzer 6.3.4. Configuring Intel® Arria® 10 and Reading .smh File with Fault Injection Debugger 6.3.5. Injecting Error with Fault Injection Debugger
7. Implementing ECC Feature in Intel® Arria® 10 ROM Design x
7.1. Examples of Error Detection and Correction
1. Overview
2. Intel® Quartus® Prime Software SEU FIT Reports
3. Intel® Arria® 10 Error Detection and Correction Feature Architecture
4. Guidelines for Error Detection CRC and Error Correction Feature
5. Guidelines for Embedded Memory ECC Feature
6. Intel® Arria® 10 EDCRC Reference Design
7. Implementing ECC Feature in Intel® Arria® 10 ROM Design
8. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
9. Document Revision History for AN 737: SEU Detection and Recovery in Intel® Arria® 10 Devices

4.3.2. Correctable and Uncorrectable Error

When an SEU is detected, you can read the EMR data to determine whether the error is correctable or uncorrectable. Intel recommends you to use Altera EMR Unloader IP core in your design. The Altera EMR Unloader IP core interprets the error and reports it at the output.

Table 5.  Correctable and Uncorrectable Error CasesThe table summarizes the correctable and uncorrectable error cases. You do not need to determine whether the current EDCRC operation is in frame-based check-bits or column-based check-bits but you need to know how to interpret the error type of the column-based or frame-based. If the EMR Unloader IP core reports the error type other than 3’b111, the error is correctable and the error will be scrubbed if you turned on internal scrubbing.
Case EDCRC Operation CRC_ERROR Pulse Column-Based Field Frame-Based Field Correctable Remark
A 1 Frame-based check-bits 1 All 0's

Type = 3'b001 or

Type = 3'b010 & bit ≠ 5'h1F or

Type = 3'b011 & bit = 5'h1F

Yes Error will be corrected if internal scrubbing is turned On
B1 Frame-based check-bits 1 All 0's

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h1F

EMR Unloader IP core will set type = 3'b111 if any of above condition met

No The frame-based check-bits will retry for 2 times and enter dead state where CRC_ERROR stays high until FPGA reconfiguration
C Stuck in dead state 1 pulse and stay high after 2nd assertion EMR Unloader IP core set Type = 3'b111 EMR Unloader IP core set type = 3'b111 No CRC_ERROR stays high until FPGA reconfiguration. Refer Case B to understand how EDCRC can stuck in dead state
D Column-based check-bits 1

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h00

EMR Unloader IP core will set type = 3'b111 if any of above condition met

All 0's No Detected uncorrectable error during column-based check-bits
E Column-based check-bits and frame-based check-bits 2

Any type except:

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h00

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h1F

EMR Unloader IP core will set type = 3'b111 if any of above condition met

No Detected uncorrectable error
F Column-based check-bits and frame-based check-bits 2

Any type except:

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h00

Any type except:

Type = 3'b111 or

Type = 3'b010 & bit = 5'h1F or

Type = 3'b011 & bit ≠ 5'h1F

Yes Error will be corrected if internal scrubbing is turned On
1 Case can occur only when the Frame-based CRC error is detected after the CRAM is configured, such as FPGA configuration, partial PR or CvP. The SEU event is statistically impossible to happen during CRAM configuration, such cases are to cover other problems such as corrupted configuration data or bad CRAM that unable to hold the correct bit setting.
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