Intel® Agilex™ Variable Precision DSP Blocks User Guide

ID 683037
Date 11/17/2022
Public

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Document Table of Contents

3.2.2.7. FP16 Vector Three Mode

This mode performs a single-precision accumulation and a summation of two half-precision multiplications.

Table 21.  Equations Applied to Vector Three Mode
Accumulate Input Vector Three with Floating-point Addition Vector Three with Floating-point Subtraction
Disable

fp32_result(t) = fp32_adder_a(t)

fp32_chainout = {fp16_mult_top_a * fp16_mult_top_b} + {fp16_mult_bot_a * fp16_mult_bot_b}

fp32_result(t) = fp32_adder_a(t)

fp32_chainout = {fp16_mult_top_a * fp16_mult_top_b} - {fp16_mult_bot_a * fp16_mult_bot_b}

Enable

fp32_result(t) = fp32_adder_a(t) + fp32_result(t-1)

fp32_chainout = {fp16_mult_top_a * fp16_mult_top_b} + {fp16_mult_bot_a * fp16_mult_bot_b}

fp32_result(t) = fp32_adder_a(t) - fp32_result(t-1)

fp32_chainout = {fp16_mult_top_a * fp16_mult_top_b} - {fp16_mult_bot_a * fp16_mult_bot_b}

The following are exception flags supported in flushed and bfloat16 formats:
  • fp16_mult_top_invalid
  • fp16_mult_top_inexact
  • fp16_mult_top_overflow
  • fp16_mult_top_underflow
  • fp16_mult_bot_invalid
  • fp16_mult_bot_inexact
  • fp16_mult_bot_overflow
  • fp16_mult_bot_underflow
  • fp16_adder_invalid
  • fp16_adder_inexact
  • fp16_adder_overflow
  • fp16_adder_underflow
  • fp32_adder_invalid
  • fp32_adder_inexact
  • fp32_adder_overflow
  • fp32_adder_underflow
The following are exception flags supported in extended format:
  • fp16_mult_top_invalid
  • fp16_mult_top_inexact
  • fp16_mult_top_infinite
  • fp16_mult_top_zero
  • fp16_mult_bot_invalid
  • fp16_mult_bot_inexact
  • fp16_mult_bot_infinite
  • fp16_mult_bot_zero
  • fp16_adder_invalid
  • fp16_adder_inexact
  • fp16_adder_infinite
  • fp16_adder_zero
  • fp32_adder_invalid
  • fp32_adder_inexact
  • fp32_adder_overflow
  • fp32_adder_underflow
Figure 38. FP16 Vector Three Mode