Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1.4. Compiling and Simulating the Design Example

Compile and simulate the design by running a simulation script from the command prompt.

  1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
    Table 2.  Steps to Simulate the Testbench
    Simulator Command
    Siemens* EDA QuestaSim* (Verilog/VHDL)

    vsim -c -do run_vsim.do

    Synopsys* VCS* (Verilog) sh run_vcs.sh
    Synopsys* VCS* MX (Verilog/VHDL) sh run_vcsmx.sh.
    Cadence* Xcelium* sh run_xcelium.sh.
  3. Analyze the results. The successful testbench sends 10 packets, receives 10 packets, and displays "Testbench complete."

The successful test run displays output confirming the following behavior:

  1. Waiting for receive (RX) clock to settle.
  2. Printing PHY status.
  3. Sending 10 packets.
  4. Receiving 10 packets.
  5. Displaying Testbench complete.

The following sample output illustrates a successful simulation test run:

#Waiting for RX alignment
#RX deskew locked
#RX lane alignment locked
#TX enabled
#**Sending Packet 1...
#**Sending Packet 2...
#**Sending Packet 3...
#**Sending Packet 4...
#**Sending Packet 5...
#**Sending Packet 6...
#**Sending Packet 7...
#**Received Packet 1...
#**Sending Packet 8...
#**Received Packet 2...
#**Sending Packet 9...
#**Received Packet 3...
#**Sending Packet 10...
#**Received Packet 4...
#**Received Packet 5...
#**Received Packet 6...
#**Received Packet 7...
#**Received Packet 8...
#**Received Packet 9...
#**Received Packet 10...
#**
#** Testbench complete.
#**
#*****************************************
After successful completion, you can analyze the results.

Section Content
Simulation Design Example Components

Level Two Title