2.5. Design Example Interface Signals
The Low Latency 40G Ethernet Intel® FPGA IP testbench for Agilex™ 5 devices is self-contained and does not require you to drive any input signals.
| Signal | Direction | Comments |
|---|---|---|
| clk50 | Input | This clock is driven by the board oscillator. The hardware design example routes this clock to the input of an IOPLL on the device and configures the IOPLL to drive a 100 MHz clock internally. |
| clk_ref_p | Input | Reference clock for GTS Transceiver. This clock signal is externally driven at 156.25 MHz. |
| tx_serial[3:0] | Output | Transceiver PHY output serial data. |
| rx_serial[3:0] | Input | Transceiver PHY input serial data. |
| tx_rst_n | Output | Reset TX PCS and MAC. Active low signal. |
| tx_rst_ack_n | Output | Reset ACK TX PCS and MAC. Active low signal. |
| rx_rst_n | Output | Reset RX PCS and MAC. Active low signal. |
| rx_rst_ack_n | Output | Reset ACK RX PCS and MAC. Active low signal. |
| csr_rst_n | Output | Reset full IP. Includes transmit and receive MACs, PCS and adapters, transceivers, as well as configuration and status registers. Active low signal. |
| csr_rst_ack_n | Output | Reset ACK for CSR reset. Active low signal. |
| user_led[7:0] | Output | Status signals. The hardware design example connects these bits to drive LEDs on the target board. Individual bits reflect the following signal values and clock behavior:
|