Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1.2. Generating the Design Example

Generate the design example from the IP Parameter Editor.
Figure 3. Example Design Tab in the Low Latency 40G Ethernet Intel® FPGA IP Parameter Editor

Follow these steps to generate the design example and testbench:

  1. In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device family and device.
  2. In the IP Catalog, locate and select Low Latency 40G Ethernet Intel® FPGA IP . The New IP Variation window appears.
  3. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, specify the parameters for your IP variation.
  6. On the Example Design tab, under Available Example Designs, select the Single Instance of IP core option.
  7. Under Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only design examples.
  8. Click the Generate Example Design button. The Select Example Design Directory window appears.
  9. If you want to modify the design example directory path or name from the defaults displayed (intel_eth_e40_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
  10. Click OK.

Section Content
Design Example Parameters

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