AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

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ID 683845
Date 8/08/2022
Public
Document Table of Contents
Document Table of Contents x
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core Design Considerations Using the Design Examples Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core x
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core Connecting the IOPLL and PLL Reconfig IP Cores Connectivity between the IOPLL and PLL Reconfig IP Cores I/O PLL Reconfiguration Write Operation I/O PLL Reconfiguration Read Operation Address Bus and Data Bus Settings .mif Streaming Reconfiguration
I/O PLL Reconfiguration Write Operation x
Write Operation for .mif Streaming Reconfiguration
Address Bus and Data Bus Settings x
Address Bus and Data Bus Setting for Counter Setting Reconfiguration Address Bus and Data Bus Setting for Dynamic Phase Shift Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration Data Bus Setting for Loop Filter and Charge Pump Settings Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
.mif Streaming Reconfiguration x
.mif File Format .mif Streaming Reconfiguration Operation Codes
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
Dynamic Phase Shift Ports in the IOPLL IP Core I/O PLL Dynamic Phase Shift Operation
Using the Design Examples x
Design Example 1: I/O PLL Reconfiguration Design Example 2: .mif Streaming Reconfiguration Design Example 3: I/O PLL Dynamic Phase Shift
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Write Operation for .mif Streaming Reconfiguration

The dynamic reconfiguration commands can also be stored in a .mif file for .mif streaming reconfiguration. To enable .mif streaming in the PLL Reconfig IP core, select the appropriate checkbox in the parameter editor and provide the path to the .mif file before generating your IP core.

To perform .mif streaming reconfiguration, follow these steps:

  1. Set the start .mif address (9'b000010000) for mgmt_address and the base address within the ROM for mgmt_writedata. To start the .mif streaming operation of I/O PLL reconfiguration, assert the mgmt_write signal for one mgmt_clk cycle.
  2. After the reconfiguration is complete, the mgmt_waitrequest signal is de-asserted.
You should not write to the start address (9'b0) in the .mif file.
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