AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

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ID 683845
Date 8/08/2022
Public
Document Table of Contents
Document Table of Contents x
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core Design Considerations Using the Design Examples Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core x
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core Connecting the IOPLL and PLL Reconfig IP Cores Connectivity between the IOPLL and PLL Reconfig IP Cores I/O PLL Reconfiguration Write Operation I/O PLL Reconfiguration Read Operation Address Bus and Data Bus Settings .mif Streaming Reconfiguration
I/O PLL Reconfiguration Write Operation x
Write Operation for .mif Streaming Reconfiguration
Address Bus and Data Bus Settings x
Address Bus and Data Bus Setting for Counter Setting Reconfiguration Address Bus and Data Bus Setting for Dynamic Phase Shift Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration Data Bus Setting for Loop Filter and Charge Pump Settings Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
.mif Streaming Reconfiguration x
.mif File Format .mif Streaming Reconfiguration Operation Codes
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
Dynamic Phase Shift Ports in the IOPLL IP Core I/O PLL Dynamic Phase Shift Operation
Using the Design Examples x
Design Example 1: I/O PLL Reconfiguration Design Example 2: .mif Streaming Reconfiguration Design Example 3: I/O PLL Dynamic Phase Shift
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Data Bus Setting for Loop Filter and Charge Pump Settings

Table 5.  Data Bus Setting for Loop Filter and Charge Pump Settings
M Counter Total Division Value Low Bandwidth Medium Bandwidth High Bandwidth
Loop Filter Setting Charge Pump Setting Loop Filter Setting Charge Pump Setting Loop Filter Setting Charge Pump Setting
Data[9..6] Data[5..0] Data[9..6] Data[5..0] Data[9..6] Data[5..0]
4–5 4’b0010 6’b001011 4’b0010 6’b011000 4’b0010 6’b010001
6–7 4’b0011 6’b010000 4’b0011 6’b001011 4’b0011 6’b011000
8–15 4’b0011 6’b010000 4’b0011 6’b011000 4’b0011 6’b100000
16–23 4’b0011 6’b001011 4’b0011 6’b010001 4’b0011 6’b001101
24–43 4’b0100 6’b010000 4’b0100 6’b011000 4’b0100 6’b100000
44–64 4’b0101 6’b010000 4’b0101 6’b011000 4’b0101 6’b100000
64–124 4’b0101 6’b011000 4’b0101 6’b100000 4’b0101 6’b101000
>125 4’b0110 6’b011000 4’b0110 6’b100000 4’b0110 6’b101000
Level Two Title