AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

ID 683845
Date 8/08/2022
Public
Document Table of Contents

I/O PLL Reconfiguration Write Operation

To perform a write operation for I/O PLL reconfiguration in the PLL Reconfig IP core, follow these steps:

  1. Set the address bus value for mgmt_address, and the data bus value for mgmt_writedata. To enable write operation for I/O PLL reconfiguration, assert the mgmt_write signal for one mgmt_clk cycle.
  2. Repeat step 1 to set the values for up to eight sets of address bus and data bus.
  3. Set the start address (9’b000000000) for mgmt_address, and any value for mgmt_writedata. To start the write operation for I/O PLL reconfiguration, assert the mgmt_write signal for one mgmt_clk cycle.
  4. After the write operation is complete, the mgmt_waitrequest signal is de-asserted.

Each dynamic reconfiguration command (address-data pair) can be of one of the three types:

  • Counter setting reconfiguration
  • Bandwidth setting reconfiguration
  • Dynamic phase shift

You can issue up to eight dynamic reconfiguration commands before triggering reconfiguration by writing to the start address. Issuing more than eight commands causes the internal reconfiguration FIFO to overflow.