AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

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ID 683838
Date 10/12/2020
Public
Document Table of Contents
Document Table of Contents x
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric x
1.1. Intel® Stratix® 10 HPS Peripherals that Support Routing to the FPGA 1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA 1.3. Document Revision History for the AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer 1.2.4. Modifying Top Level File 1.2.5. Adding Pin Assignments for SPIM0 1.2.6. Hardware Programming File Compilation and Generation 1.2.7. Building U-Boot 1.2.8. Preparing QSPI Image 1.2.9. Building Linux 1.2.10. Building Yocto Rootfs 1.2.11. Building spidev Test Program 1.2.12. Creating SD Card Image 1.2.13. Booting the Board 1.2.14. Testing the SPIM0
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

1.2.4. Modifying Top Level File

  1. In the ghrd_s10_top.v, add the top level signals connecting to SPI.
    Note: Only a partial view displayed, below. 
    module ghrd_s10_top (
output wire spi_clk,
output wire spi_cs,
output wire spi_mosi,
input  wire spi_miso,
  2. Connect the relevant Platform Designer exported signals to the top level signals:
    Note: Only a partial view displayed, below. 
    qsys_top soc_inst (
.s10_hps_spim0_sclk_out_clk            (spi_clk),
.spi_cs_pio_external_connection_export (spi_cs),
.s10_hps_spim0_mosi_o                  (spi_mosi),
.s10_hps_spim0_miso_i                  (spi_miso),
.s10_hps_spim0_ss_in_n                 (1'b1),
Level Two Title