AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

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ID 683838
Date 10/12/2020
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Document Table of Contents
Document Table of Contents x
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric x
1.1. Intel® Stratix® 10 HPS Peripherals that Support Routing to the FPGA 1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA 1.3. Document Revision History for the AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer 1.2.4. Modifying Top Level File 1.2.5. Adding Pin Assignments for SPIM0 1.2.6. Hardware Programming File Compilation and Generation 1.2.7. Building U-Boot 1.2.8. Preparing QSPI Image 1.2.9. Building Linux 1.2.10. Building Yocto Rootfs 1.2.11. Building spidev Test Program 1.2.12. Creating SD Card Image 1.2.13. Booting the Board 1.2.14. Testing the SPIM0
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

1.1. Intel® Stratix® 10 HPS Peripherals that Support Routing to the FPGA

The following types of Intel® Stratix® 10 HPS peripherals are capable of routing to the FPGA fabric:

  • Secure Digital/Multimedia Card (SD/MMC)
  • Ethernet Media Access Controller (EMAC)
  • Serial Peripheral Interface (SPI)
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Inter-Integrated Circuit (I2C)
  • NAND Flash Controller
  • TRACE Interface

In many cases, routing the HPS IP signals to the FPGA external interface allows more signals to be exposed.

Table 1.  Peripherals that Support Signal Routing from the HPS Domain to FPGA DomainThe following table lists the interface type that is available depending on whether the IP interface is pinned out in the HPS domain or the FPGA domain.
Peripherals Interface Description

HPS Domain

FPGA Domain

SD/MMC Standard SD/MMC interface with up to 8-bit data bus Standard SD/MMC interface, including:
  • Up to 8-bit data bus
  • Card detect interface
  • Card interrupt
  • Voltage switching
  • Power enable
  • Reset 1

EMAC

RMII and RGMII Interface

MII, GMII, RMII, RGMII, SGMII

SPI Master

MOSI/MISO SPI interface configurable to single or dual slaves

MOSI/MISO SPI interface with output enables that support up to four slaves; interface achieved by connecting exported signals to bidirectional buffers

SPI Slave

MOSI/MISO SPI interface configurable to single master

MOSI/MISO SPI interface configurable to single master with output enables

UART

Standard UART interface with flow control signals

Standard UART interface with flow control signals, including DSR, DCD, RI, and DTR; and two user-defined output signals are also available

I2C

Standard I2C interface

Standard I2C interface achieved by connecting exported signals to a bidirectional buffer

NAND Flash Controller Standard NAND Interface with 8- or 16-bit of data and one set of CE and R/B signals Standard NAND Interface with 8- or 16-bit of data and four sets of CE and R/B signals
TRACE TRACE debug interface TRACE debug interface

For a description of each of the peripheral signal interfaces listed above, refer to the corresponding chapters in the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.

Related Information
1 The SD/MMC controller does not directly support reset, voltage switching, card interrupts, power enable or write protect functions. However, you can connect these signals to general-purpose I/Os (GPIOs).
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