AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

Download PDF
ID 683838
Date 10/12/2020
Public
Document Table of Contents
Document Table of Contents x
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric x
1.1. Intel® Stratix® 10 HPS Peripherals that Support Routing to the FPGA 1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA 1.3. Document Revision History for the AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric
1.2. Design Example: Intel® Stratix® 10 HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer 1.2.4. Modifying Top Level File 1.2.5. Adding Pin Assignments for SPIM0 1.2.6. Hardware Programming File Compilation and Generation 1.2.7. Building U-Boot 1.2.8. Preparing QSPI Image 1.2.9. Building Linux 1.2.10. Building Yocto Rootfs 1.2.11. Building spidev Test Program 1.2.12. Creating SD Card Image 1.2.13. Booting the Board 1.2.14. Testing the SPIM0
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1. AN 923: Routing Intel® Stratix® 10 HPS Peripherals to FPGA Fabric

1.2.5. Adding Pin Assignments for SPIM0

In ghrd_1sx280lu2f50e2vg.qsf, connect the top level signals to the correct pins on the Intel® Stratix® 10 SoC development kit, and set them to 1.8V: 
set_location_assignment PIN_BD28 -to spi_clk
set_location_assignment PIN_BF26 -to spi_cs
set_location_assignment PIN_BC28 -to spi_mosi
set_location_assignment PIN_BE27 -to spi_miso
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk -entity\
 ghrd_s10_top
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_cs -entity\
 ghrd_s10_top
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi -entity\
 ghrd_s10_top
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso -entity\
 ghrd_s10_top
Level Two Title