Visible to Intel only — GUID: wtw1430306652121
Ixiasoft
Visible to Intel only — GUID: wtw1430306652121
Ixiasoft
5.1. Voltage Controller Core Registers
Offset | Register Name | Bits | Bit Name | RO/RW | Description | Reset Value |
---|---|---|---|---|---|---|
0x0 | Command | 13..31 | Reserved | — | Reserved. | 0x0 |
12 | CAL | RW | Determines whether the output data is using a calibrated or a non-calibrated value.
You must not use this bit to enable calibration. |
0x0 | ||
11 | BU1 | RW | Unipolar selection for Channel 0 or 1.1
|
0x0 | ||
10 | BU0 | RW | 0x0 | |||
9 | MD1 | RW | Mode select for channel sequencer.
|
0x0 | ||
8 | MD0 | RW | 0x0 | |||
7 | Reserved | — | Reserved. | 0x0 | ||
4:6 | CHSEL | RW | Specifies the channel to be converted and used when MD[1:0] = 2'b11. | 0x0 | ||
3 | Reserved | — | Reserved. | 0x0 | ||
1:2 | MODE | RW | Specifies the controller core's mode of operation.
Do not write to this address when the RUN bit is set. You must wait for the hardware to clear these bits before updating this address. |
0x0 | ||
0 | RUN | RW | Control bit to trigger the sequencer core operation.
When the Intel® Quartus® Prime software writes a 0 to this address, the controller core completes its current operation and clears this field. |
0x0 |