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1. Intel® FPGA Voltage Sensor IP Core Overview
2. Intel® FPGA Voltage Sensor IP Core Getting Started
3. Intel® FPGA Voltage Sensor IP Core Functional Description
4. Intel® FPGA Voltage Sensor IP Core Interface Signals
5. Intel® FPGA Voltage Sensor IP Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide
7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide
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6.1.1. Accessing the Voltage Sensor Using FPGA Core Access
In user mode, you can implement a soft IP to access the voltage sensor block. To access the voltage sensor block from the core fabric, include the following WYSIWYG atom in your Intel® Quartus® Prime project:
WYSIWYG Atom to Access the Voltage Sensor Block
twentynm_vsblock<name>
(
.clk (<input>, clock signal from core),
.reset(<input>, reset signal from core),
.corectl(<input>, core enable signal from core),
.coreconfig(<input>, config signal from core),
.confin(<input>, config data signal from core),
.chsel(<input>, 4 bits channel selection signal from core),
.eoc(<output>, end of conversion signal from vsblock),
.eos(<output>, end of sequence signal from vsblock),
.dataout(<output>, 12 bits data out of vsblock)
);
Port Name | Type | Description |
---|---|---|
clk | Input | Clock signal from the core. The voltage sensor supports up to an 11-MHz clock. |
reset | Input | Active high reset signal. An asynchronous high-to-low transition on the reset signal starts voltage sensor conversion. All registers are cleared and the internal voltage sensor clock is gated off when the reset signal is high. |
corectl | Input | Active high signal. "1" indicates the voltage sensor is enabled for core access. "0" indicates the voltage sensor is disabled for core access. |
coreconfig | Input | Serial configuration signal. Active high. |
confin | Input | Serial input data from the core to configure the configuration register. The configuration register for the core access mode is 8 bits wide. The LSB is the first bit shifted in. |
chsel[3:0] | Input | 4-bit channel address. Specifies the channel to be converted. |
eoc | Output | Indicates the end of the conversion. This signal is asserted after the conversion of each channel data packet. |
eos | Output | Indicates the end of sequence. This signal is asserted for one cycle after the completion of the conversion of the selected sequence. |
dataout[11:0] | Output |
|