Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

Download PDF
ID 683686
Date 1/11/2022
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the SR-IOV Design Example 3. Parameter Settings 4. Physical Layout 5. Interfaces and Signal Descriptions 6. Registers 7. Programming and Testing SR-IOV Bridge MSI Interrupts 8. Error Handling 9. IP Core Architecture 10. Design Implementation 11. Debugging 12. Document Revision History A. Transaction Layer Packet (TLP) Header Formats B. Intel® Arria® 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
1. Datasheet x
1.1. Intel® Arria® 10 Avalon® -ST Interface with SR-IOV for PCI Express* Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Debug Features 1.5. IP Core Verification 1.6. Performance and Resource Utilization 1.7. Recommended Speed Grades for SR-IOV Interface
1.1. Intel® Arria® 10 Avalon® -ST Interface with SR-IOV for PCI Express* Datasheet x
1.1.1. SR-IOV Features
1.5. IP Core Verification x
1.5.1. Compatibility Testing Environment
2. Getting Started with the SR-IOV Design Example x
2.1. Directory Structure for Intel® Arria® 10 SR-IOV Design Example 2.2. Design Components for the SR-IOV Design Example 2.3. Generating the SR-IOV Design Example 2.4. Compiling and Simulating the Design for SR-IOV
3. Parameter Settings x
3.1. Parameters 3.2. Intel® Arria® 10 Avalon-ST Settings 3.3. Intel® Arria® 10 SR-IOV System Settings 3.4. Base Address Register (BAR) Settings 3.5. SR-IOV Device Identification Registers 3.6. Intel® Arria® 10 Interrupt Capabilities 3.7. Physical Function TLP Processing Hints (TPH) 3.8. Address Translation Services (ATS) 3.9. PCI Express and PCI Capabilities Parameters 3.10. PHY Characteristics 3.11. Example Designs
3.9. PCI Express and PCI Capabilities Parameters x
3.9.1. PCI Express and PCI Capabilities 3.9.2. Error Reporting 3.9.3. Link Capabilities 3.9.4. Slot Capabilities 3.9.5. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Intel® Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Intel® Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. Interfaces and Signal Descriptions x
5.1. Avalon-ST TX Interface 5.2. Component-Specific Avalon-ST Interface Signals 5.3. Avalon-ST RX Interface 5.4. BAR Hit Signals 5.5. Configuration Status Interface 5.6. Clock Signals 5.7. Function-Level Reset (FLR) Interface 5.8. SR-IOV Interrupt Interface 5.9. Configuration Extension Bus (CEB) Interface 5.10. Implementing MSI-X Interrupts 5.11. Control Shadow Interface 5.12. Local Management Interface (LMI) Signals 5.13. Reset, Status, and Link Training Signals 5.14. Hard IP Reconfiguration Interface 5.15. Serial Data Signals 5.16. Test Signals 5.17. PIPE Interface Signals 5.18. Intel® Arria® 10 Development Kit Conduit Interface
5.9. Configuration Extension Bus (CEB) Interface x
5.9.1. Vital Product Data (VPD) Capability
5.9.1. Vital Product Data (VPD) Capability x
5.9.1.1. Determine the Pointer Address of an External Capability Register 5.9.1.2. VPD Capability Implementation
6. Registers x
6.1. Addresses for Physical and Virtual Functions 6.2. Correspondence between Configuration Space Registers and the PCIe Specification 6.3. PCI and PCI Express Configuration Space Registers 6.4. MSI Registers 6.5. MSI-X Capability Structure 6.6. Power Management Capability Structure 6.7. PCI Express Capability Structure 6.8. Advanced Error Reporting (AER) Enhanced Capability Header Register 6.9. Uncorrectable Error Status Register 6.10. Uncorrectable Error Mask Register 6.11. Uncorrectable Error Severity Register 6.12. Correctable Error Status Register 6.13. Correctable Error Mask Register 6.14. Advanced Error Capabilities and Control Register 6.15. Header Log Registers 0-3 6.16. SR-IOV Virtualization Extended Capabilities Registers 6.17. Virtual Function Registers
6.3. PCI and PCI Express Configuration Space Registers x
6.3.1. Type 0 Configuration Space Registers 6.3.2. PCI and PCI Express Configuration Space Register Content 6.3.3. Interrupt Line and Interrupt Pin Register
6.16. SR-IOV Virtualization Extended Capabilities Registers x
6.16.1. SR-IOV Virtualization Extended Capabilities Registers Address Map 6.16.2. ARI Enhanced Capability Header 6.16.3. SR-IOV Enhanced Capability Registers 6.16.4. Initial VFs and Total VFs Registers 6.16.5. VF Device ID Register 6.16.6. Page Size Registers 6.16.7. VF Base Address Registers (BARs) 0-5 6.16.8. Secondary PCI Express Extended Capability Header 6.16.9. Lane Status Registers 6.16.10. Transaction Processing Hints (TPH) Requester Enhanced Capability Header
7. Programming and Testing SR-IOV Bridge MSI Interrupts x
7.1. Setting Up and Verifying MSI Interrupts 7.2. Masking MSI Interrupts 7.3. Dropping a Pending MSI Interrupt
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
9. IP Core Architecture x
9.1. PCI Express Protocol Stack 9.2. Data Link Layer 9.3. Physical Layer 9.4. Top-Level Interfaces 9.5. Intel® Arria® 10 Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
9.4. Top-Level Interfaces x
9.4.1. Avalon-ST Interface 9.4.2. Clocks and Reset 9.4.3. Interrupts 9.4.4. PIPE
10. Design Implementation x
10.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 10.2. Recommended Reset Sequence to Avoid Link Training Issues 10.3. SDC Timing Constraints
11. Debugging x
11.1. Setting Up Simulation 11.2. Simulation Fails To Progress Beyond Polling.Active State 11.3. Hardware Bring-Up Issues 11.4. Link Training 11.5. Creating a Signal Tap Debug File to Match Your Design Hierarchy 11.6. Use Third-Party PCIe Analyzer 11.7. BIOS Enumeration Issues
11.1. Setting Up Simulation x
11.1.1. Changing Between Serial and PIPE Simulation 11.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants 11.1.3. Viewing the Important PIPE Interface Signals 11.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 11.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
12. Document Revision History x
12.1. Document Revision History for the Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
1. Datasheet
2. Getting Started with the SR-IOV Design Example
3. Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Programming and Testing SR-IOV Bridge MSI Interrupts
8. Error Handling
9. IP Core Architecture
10. Design Implementation
11. Debugging
12. Document Revision History
A. Transaction Layer Packet (TLP) Header Formats
B. Intel® Arria® 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive

3.3. Intel® Arria® 10 SR-IOV System Settings

Parameter

Value

Description

Total Physical Functions (PFs) :

1 - 8

This core supports 1 - 8 Physical Functions.

Total Virtual Functions of Physical Function0 (PF0 VFs) - Total Virtual Functions of Physical Function7 (PF7 VFs):

0 - 2048

Total number of VFs assigned to a PF. You can assign VFs in the following granularities:
  • Granularity of 1 for 1-8 VFs
  • Granularity of 4 for 8-256 VFs
  • Granularity of 64 for 256-1024 VFs
  • Granularity of 512 for 1024-2048 VFs
The sum of VFs assigned to all PFs cannot exceed the 2048 VF total.
Note: The granularity restriction for assigning VFs applies to both the total VFs of each individual PF as well as the sum of all VFs across all enabled PFs. See the example and snapshot following this table for more details.
System Supported Page Size: 4KB - 4MB Specifies the pages sizes supported. Sets the Supported Page Sizes register of the SR-IOV Capability structure.
Enable SR-IOV Support

On/Off

When On, the variant supports multiple PFs and VFs. When Off, .supports PFs only.

Enable Alternative Routing-ID (ARI) support

On/Off

When On, ARI supports up to 256 functions. Refer to Section 6.1.3 Alternative Routing-ID Interpretation (ARI) of the PCI Express Base Specification for more information about ARI.

Enable Functional Level Reset (FLR)

On/Off

When On, each function has its own, individual reset.
Enable TLP Processing Hints (TPH) support for PFs On/Off When On, the variant includes the TPH registers to help you improve latency and traffic congestion.
Enable TLP Processing Hints (TPH) support for VFs
Enable Address Translation Services (ATS) support for PFs On/Off When On, the variant includes the ATS registers.
Enable Address Translation Services (ATS) support for VFs
Enable PCI Express Extended Space (CEB) On/Off When On, the IP core variant includes the optional Configuration Extension Bus (CEB) interface. This interface provides a way to add extra capabilities on top of those available in the internal configuration space of the SR-IOV Bridge.1
CEB PF External Standard Capability Pointer Address (DW Address in Hex) 0x0 Specifies the address for the next pointer field of the last capability structure within the SR-IOV bridge for the physical function. It allows the internal PCI Compatible region capability to point to the capability implemented in user logic and establish the link list for the first 256 bytes in the register address space.
CEB PF External Extended Capability Pointer Address (DW Address in Hex) 0x0

Specifies the address for the next pointer field of the last capability structure within the SR-IOV bridge for the physical function. It allows the internal PCI Compatible region capability to point to the capability implemented in user logic and establish the link list for the PCIe extended configuration space.

Supports the address range from 0x100 (DW address) or 0x400 (byte address) and beyond.

CEB VF External Standard Capability Pointer Address (DW Address in Hex) 0x0 Specifies the address for the next pointer field of the last capability structure within the SR-IOV bridge for the virtual function. It allows the internal PCI Compatible region capability to point to the capability implemented in user logic and establish the link list for the first 256 bytes in the register address space.
CEB VF External Extended Capability Pointer Address (DW Address in Hex) 0x0

Specifies the address for the next pointer field of the last capability structure within the SR-IOV bridge for the virtual function. It allows the internal PCI Compatible region capability to point to the capability implemented in user logic and establish the link list for the PCIe extended configuration space.

Supports the address range from 0x100 (DW address) or 0x400 (byte address) and beyond.

CEB REQ to ACK Latency (in Clock Cycles) 1 - 7

Specifies the timeout value for the request issued on the CEB interface. The SR-IOV bridge will send a completion with all zeros in the data and completion status field back to the host after the timeout.

Note: A large ACK latency time may result in a bandwidth degradation.

The granularity restriction for assigning VFs applies to both the total VFs of each individual PF as well as the sum of all VFs across all enabled PFs. For example, the setting in the snapshot below is invalid since the sum of all VFs assigned to all PFs (i.e, 268 VFs) is not a multiple of 64 and therefore does not meed the granularity restriction even though the VF counts of individual PFs are valid (i.e, they are multiples of 4).

Related Information
1 To implement user capabilities registers, Intel recommends that you use an open address space in the configuration space across all available Physical Functions (PFs) and Virtual Functions (VFs). Developing user capabilities registers for individual PFs or VFs is not possible.
Level Two Title