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1. Datasheet
2. Getting Started with the SR-IOV Design Example
3. Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Programming and Testing SR-IOV Bridge MSI Interrupts
8. Error Handling
9. IP Core Architecture
10. Design Implementation
11. Debugging
12. Document Revision History
A. Transaction Layer Packet (TLP) Header Formats
B. Intel® Arria® 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
3.1. Parameters
3.2. Intel® Arria® 10 Avalon-ST Settings
3.3. Intel® Arria® 10 SR-IOV System Settings
3.4. Base Address Register (BAR) Settings
3.5. SR-IOV Device Identification Registers
3.6. Intel® Arria® 10 Interrupt Capabilities
3.7. Physical Function TLP Processing Hints (TPH)
3.8. Address Translation Services (ATS)
3.9. PCI Express and PCI Capabilities Parameters
3.10. PHY Characteristics
3.11. Example Designs
4.1. Hard IP Block Placement In Intel® Cyclone® 10 GX Devices
4.2. Hard IP Block Placement In Intel® Arria® 10 Devices
4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates
4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate
4.5. PCI Express Gen3 Bank Usage Restrictions
5.1. Avalon-ST TX Interface
5.2. Component-Specific Avalon-ST Interface Signals
5.3. Avalon-ST RX Interface
5.4. BAR Hit Signals
5.5. Configuration Status Interface
5.6. Clock Signals
5.7. Function-Level Reset (FLR) Interface
5.8. SR-IOV Interrupt Interface
5.9. Configuration Extension Bus (CEB) Interface
5.10. Implementing MSI-X Interrupts
5.11. Control Shadow Interface
5.12. Local Management Interface (LMI) Signals
5.13. Reset, Status, and Link Training Signals
5.14. Hard IP Reconfiguration Interface
5.15. Serial Data Signals
5.16. Test Signals
5.17. PIPE Interface Signals
5.18. Intel® Arria® 10 Development Kit Conduit Interface
6.1. Addresses for Physical and Virtual Functions
6.2. Correspondence between Configuration Space Registers and the PCIe Specification
6.3. PCI and PCI Express Configuration Space Registers
6.4. MSI Registers
6.5. MSI-X Capability Structure
6.6. Power Management Capability Structure
6.7. PCI Express Capability Structure
6.8. Advanced Error Reporting (AER) Enhanced Capability Header Register
6.9. Uncorrectable Error Status Register
6.10. Uncorrectable Error Mask Register
6.11. Uncorrectable Error Severity Register
6.12. Correctable Error Status Register
6.13. Correctable Error Mask Register
6.14. Advanced Error Capabilities and Control Register
6.15. Header Log Registers 0-3
6.16. SR-IOV Virtualization Extended Capabilities Registers
6.17. Virtual Function Registers
6.16.1. SR-IOV Virtualization Extended Capabilities Registers Address Map
6.16.2. ARI Enhanced Capability Header
6.16.3. SR-IOV Enhanced Capability Registers
6.16.4. Initial VFs and Total VFs Registers
6.16.5. VF Device ID Register
6.16.6. Page Size Registers
6.16.7. VF Base Address Registers (BARs) 0-5
6.16.8. Secondary PCI Express Extended Capability Header
6.16.9. Lane Status Registers
6.16.10. Transaction Processing Hints (TPH) Requester Enhanced Capability Header
11.1.1. Changing Between Serial and PIPE Simulation
11.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants
11.1.3. Viewing the Important PIPE Interface Signals
11.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
11.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
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9.1. PCI Express Protocol Stack
The Intel® Arria® 10 Hard IP for PCI Express with SR-IOV implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification. The protocol stack includes the following layers:
- Transaction Layer—The Transaction Layer contains the Configuration Space, which manages communication with the Application Layer, the RX and TX channels, the RX buffer, and flow control credits.
- Data Link Layer—The Data Link Layer, located between the Physical Layer and the Transaction Layer, manages packet transmission and maintains data integrity at the link level. Specifically, the Data Link Layer performs the following tasks:
- Manages transmission and reception of Data Link Layer Packets (DLLPs)
- Generates all transmission cyclical redundancy code (CRC) values and checks all CRCs during reception
- Manages the retry buffer and retry mechanism according to received ACK/NAK Data Link Layer packets
- Initializes the flow control mechanism for DLLPs and routes flow control credits to and from the Transaction Layer
- Physical Layer—The Physical Layer initializes the speed, lane numbering, and lane width of the PCI Express link according to packets received from the link and directives received from higher layers.
The following figure provides a high‑level block diagram.
Figure 51. Intel® Arria® 10 Hard IP for PCI Express with SR-IOV
Lanes |
Gen1 |
Gen2 |
Gen3 |
---|---|---|---|
×4 |
N/A | N/A |
125 MHz @ 256 bits |
×8 |
N/A |
125 MHz @ 256 bits |
250 MHz @ 256 bits |
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