Visible to Intel only — GUID: mjr1593679301378
Ixiasoft
Visible to Intel only — GUID: mjr1593679301378
Ixiasoft
2.3. eSRAM Intel® FPGA IP v19.1.4
Intel® Quartus® Prime Version | Description | Impact |
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20.2 | Renamed the I/O PLL filename to waive the warning message from the IOPLL file. If the two eSRAMs have the same PLL parameters (PLL reference clock frequency and PLL desired clock frequency), the warning message can be ignored. If the two eSRAMs have different PLL parameters, after compilation they will be set to the same PLL frequencies taken from one of the eSRAM Intel® FPGA IP parameters. Refer to the Quartus Fitter report > Plan Stage > PLL Usage Summary to observe the implemented eSRAM IOPLL frequencies. IP update is needed when the PLL parameter for both eSRAM is different. |
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