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1.1. eSRAM Intel Agilex® 7 FPGA IP v20.1.0
1.2. eSRAM Intel Agilex® 7 FPGA IP v20.0.0
1.3. eSRAM Intel Agilex® 7 FPGA IP v19.2.1
1.4. eSRAM Intel Agilex® 7 FPGA IP v19.2.0
1.5. eSRAM Intel Agilex® 7 FPGA IP v19.1.2
1.6. eSRAM Intel Agilex® 7 FPGA IP v19.1.1
1.7. Intel Agilex® 7 Embedded Memory User Guide Archives
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Ixiasoft
1.2. eSRAM Intel Agilex® 7 FPGA IP v20.0.0
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
21.3 | Updated the ch{0-7}_ecc_dec_eccmode and ch{0-7}_ecc_enc_eccmode parameters to ECC_DISABLED for unused ports. | IP upgrade is required to obtain the design pass compilation with Intel® Quartus® Prime Pro Edition software version 21.3. |