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1.1. eSRAM Intel Agilex® 7 FPGA IP v20.1.0
1.2. eSRAM Intel Agilex® 7 FPGA IP v20.0.0
1.3. eSRAM Intel Agilex® 7 FPGA IP v19.2.1
1.4. eSRAM Intel Agilex® 7 FPGA IP v19.2.0
1.5. eSRAM Intel Agilex® 7 FPGA IP v19.1.2
1.6. eSRAM Intel Agilex® 7 FPGA IP v19.1.1
1.7. Intel Agilex® 7 Embedded Memory User Guide Archives
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1.3. eSRAM Intel Agilex® 7 FPGA IP v19.2.1
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
21.2 | Fixed the hold violation by adding (* altera_attribute = "-name HYPER_REGISTER_DELAY_CHAIN 100"*) to the eSRAM Intel Agilex® 7 FPGA IP. | The change is optional. You are required to perform an IP upgrade if your IP cannot meet the maximum performance specification due to a hold violation. |