AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices

Download PDF
ID 683511
Date 5/28/2019
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 890: JESD204B Intel FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix 10 L-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices

1.3.2. Transmitter Transport Layer

To verify the data integrity of the payload data stream through the transmitter (TX) JESD204B Intel® FPGA IP and transport layer, the DAC JESD core is configured to check the short transport layer (STPL) test pattern that is transmitted from the FPGA’s test pattern generator. The DAC JESD core checks the transport layer test patterns based on the F = 1, 2, 3, 4, or 8 configuration. The STPL test pattern has a duration of one frame period and is repeated continuously for the duration of the test.

To verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, the FPGA is configured to generate a sine wave. An oscilloscope is used to observe the waveform at the DAC analog channels.

Figure 3. Data Integrity Check Using Short Transport Layer Test Pattern CheckerThis figure shows the conceptual test setup for data integrity checking.

The Signal Tap logic analyzer monitors the operation of the TX transport layer.

Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria

TL.1

 Check the transport layer mapping using the STPL test pattern.

The following signals in altera_jesd204_transport_tx_top.sv are tapped:

  • jesd204_tx_data_valid
  • jesd204_tx_data_ready

The following signal in altera_jesd204_ed_RX_TX.sv is tapped:

  • jesd204_tx_int

The txframe_clk signal is used as the sampling clock for the Signal Tap logic analyzer.

Check the following in the DAC:

  • STPL test status
  • The jesd204_tx_data_ready and jesd204_tx_data_valid signals are asserted.
  • The STPL test status in DAC register 0x32F for all DACs does not show an error.
  • The jesd204_tx_int signal is deasserted if there is no error.

TL.2

 Verify the data transfer from digital to analog domain.

Enable the sine wave generator in the FPGA and observe the DAC analog channel output on the oscilloscope.

A monotone sine wave is observed on the oscilloscope.
Level Two Title