1.8. Appendix
Device Used and Quartus Tool Version
The Intel® Stratix® 10 1SX280LU2F50E2VGS3 device (transceiver speed grade -2 device) is used.
The Intel® Quartus® Prime Pro Edition software version 18.1.0 Build 222 is used for compilation of designs.
Timing Closure Details
Synthesis/Fitter Settings:
The following Analysis/Fitter settings were added to the Quartus Settings File (.qsf) to close the timing requirements for some parameter configuration modes.
| Compiler Setting | Value Used | Default Value |
|---|---|---|
| Optimization Technique | Speed | Balanced |
| Router Timing Optimization Level | Maximum | Normal |
| Auto Packed Registers | Normal | Auto |
| Physical Synthesis | ON | OFF |
| Restructure Multipliers | OFF | Auto |
Known Issues/Warnings
In some parameter configuration modes, sysref_in is listed in the unconstrained paths. In addition, the warning ”sysref_in was determined to be a clock but was found without an associated clock assignment” is encountered. This warning occurs because the clock measure module is used to measure the SYSREF frequency. The clock measure module measures the exact SYSREF frequency generated by the HMC7044 clock generator in the AD9174 EVM for the FPGA and DAC.
The HMC7044 clock generator in the AD9174 EVM and the PLL in the AD9174 device are used to generate the DAC sample rate (DAC sampling clock). The output clock generated by the HMC7044 clock generator is in multiples of 122.88 MHz. In addition, only the SPI_WRITE command is applicable to the HMC7044 registers while the SPI_READ command is not supported. Consequently, the lane rate is fixed to 14.7456 Gbps with a reference clock of 368.64 MHz (multiple of 122.88 MHz) and not 15 Gbps with a reference clock of 375 MHz.
These known issues/warnings do not have any material impact on the test results.