AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices

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ID 683511
Date 5/28/2019
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Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 890: JESD204B Intel FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix 10 L-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices

1.4. JESD204B Intel FPGA IP and DAC Configurations

The JESD204B Intel® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the AD9174 device's configuration registers. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9174 operating conditions.

The hardware checkout testing implements the JESD204B Intel® FPGA IP with the following parameter configurations.

Table 6.  Parameter Configuration
Mode LMF N/N' S Channel per DAC Interpolation DAC Rate (Msps) Data Rate (Msps) Lane Rate (Mbps) FPGA Device Clock (MHz)4 FPGA Link Clock (MHz)5 FPGA Frame Clock (MHz)5 Data Pattern6 7 8
0 124 16 1 1 16 5898.24 3686.4 14745.6 368.64 368.64 368.64

Sine, single pulse, constant,

M0S0 – 0xFEBC, M1S0 – 0xA5ED
1 244 16 1 2 32 11796.48 3686.4 14745.6 368.64 368.64 368.64

Sine, single pulse, constant,

M0S0 – 0xF1E2, M1S0 – 0xD3C4, M2S0 – 0xB5A6, M3S0 – 0x9780
2 364 16 1 3 32 11796.48 3686.4 14745.6 368.64 368.64 368.64

Sine, single pulse,

constant,

M0S0 – 0xF1E2, M1S0 – 0xD3C4, M2S0 – 0xB5A6, M3S0 – 0x9780, M4S0 – 0xFEBC , M5S0 – 0xA5ED

3 222 16 1 1 8 5898.24 7372.8 14745.6 368.64 368.64 368.64

Sine, single pulse,

constant,

M0S0 – 0xFEBC, M1S0 – 0xA5ED
4 442 16 1 2 16 11796.48 7372.8 14745.6 368.64 368.64 368.64

Sine, single pulse, constant,

M0S0 – 0xF1E2, M1S0 – 0xD3C4, M2S0 – 0xB5A6, M3S0 – 0x9780
5 123 12 1 1 12 5898.24 4915.2 14745.6 368.64 368.64 245.76

Sine, single pulse, constant,

M0S0 – 0xFEB, M1S0 – 0xA5E
6 243 12 1 2 24 11796.48 4915.2 14745.6 368.64 368.64 245.76

Sine, single pulse,

constant,

M0S0 – 0xF1E, M1S0 – 0xD3C, M2S0 – 0x5EC, M3S0 – 0xA3D
7 148 16 1 2 64 11796.48 1843.20 14745.6 368.64 368.64 184.32

Sine, single pulse,

constant,

M0S0 – 0xF1E2, M1S0 – 0xD3C4, M2S0 – 0xB5A6, M3S0 – 0x9780
8 421 16 1 1 8 11796.48 1474.56 14745.6 368.64 368.64 368.64

Sine, single pulse, constant,

M0S0 – 0xFEBC, M1S0 – 0xA5ED
9 422 16 2 1 8 11796.48 1474.56 14745.6 368.64 368.64 368.64

Sine, single pulse,

constant,

M0S0 – 0xF1E2, M0S1 – 0xD3C4, M1S0 – 0xB5A6, M1S1 – 0x9780
10 821 16 2 1 4 11796.48 2949.12 14745.6 368.64 368.64 368.64

Sine, single pulse, constant,

M0S0 – 0xF1E2, M0S1 – 0xD3C4, M1S0 – 0xB5A6, M1S1 – 0x9780
11 822 16 4 1 4 11796.48 2949.12 14745.6 368.64 368.64 368.64

Sine, single pulse, constant,

M0S0 – 0xF1E2, M0S1 – 0xD3C4, M0S2 – 0xB5A6, M0S3 – 0x9780, M1S0 – 0x5ECB, M1S1 – 0xAED5, M1S2 – 0x49AD, M1S3 – 0xF1BC

12 823 12 8 1 2 5898.24 2949.12 11059.2 368.64 276.48 184.32

Sine, single pulse,

constant,

M0S0 – 0xF1E, M0S1 – 0xD3C, M0S2 – 0xB5A, M0S3 – 0x978, M0S4 – 0x5EC, M0S5 – 0xAED, M0S6 – 0x49A, M0S7 – 0xF1B, M1S0 – 0xF50, M1S1 – 0xD6E, M1S2 – 0xB8C, M1S3 – 0x9AA, M1S4 – 0x61E, M1S5 – 0xB1F, M1S6 – 0x4CC, M1S7 – 0xF4D

18 411 16 2 1 1 2949.12 2949.12 14745.6 368.64 368.64 368.64

Sine, single pulse,

constant,

M0S0 – 0xFEBC, M1S0 – 0xA5ED
19 412 16 4 1 1 2949.12 2949.12 14745.6 368.64 368.64 368.64

Sine, single pulse,

constant,

M0S0 – 0xF1E2, M0S1 – 0xD3C4, M0S2 – 0xB5A6, M0S3 – 0x9780, M0S4 – 0x5ECB, M0S5 – 0xAED5, M0S6 – 0x49AD, M0S7 – 0xF1BC

20 811 16 4 1 1 5898.24 5898.24 14745.6 368.64 368.64 368.64

Sine, single pulse,

constant,

M0S0 – 0xF1E2, M0S1 – 0xD3C4, M0S2 – 0xB5A6, M0S3 – 0x9780
21 812 16 8 1 1 5898.24 5898.24 14745.6 368.64 368.64 368.64

Sine, single pulse, constant,

M0S0 – 0xF1E2, M0S1 – 0xD3C4, M0S2 – 0xB5A6, M0S3 – 0x9780, M0S4 – 0x5ECB, M0S5 – 0xAED5, M0S6 – 0x49AD, M0S7 – 0xF1BC

22 423 12 4 1 6 11796.48 1966.08 14745.6 368.64 368.64 245.76

Sine, single pulse, constant,

M0S0 – 0xF1E, M0S1 – 0xD3C, M0S2 – 0xB5A, M0S3 – 0x978, M1S0 – 0x5EC, M1S1 – 0xAED, M1S2 – 0x49A, M1S3 – 0xF1B

4 The device clock is used to clock the transceiver.
5 The link clock and frame clock are derived from the device clock using an internal PLL.
6 The sine wave pattern is used in the TL.2 and SCR.2 test cases to verify that the pattern generated in the FPGA transport layer is transmitted by the DAC analog channel.
7 The single pulse pattern is used in the deterministic latency test cases DL.1 and DL.2 only.
8 The constant pattern is used for the STPL test.
Level Two Title