| Added a note clarifying that the Autonomous Hard IP mode is enabled by default for all Intel® Stratix® 10 IPs for PCI Express* . |
This mode enables the PCIe IPs to communicate with the Host before the FPGA configuration and entry into User mode are complete. This mode cannot be disabled in Intel® Stratix® 10 devices. |
| Added a note clarifying that the Control Shadow Interface of the Intel® Stratix® 10 Avalon® -ST IP for PCI Express* is only used to access Virtual Function (VF) registers and not Physical Function (PF) registers. |
The Control Shadow Interface provides access to the current settings for some of the VF Control Register fields in the PCI and PCI Express Configuration Spaces located in the SR-IOV Bridge. This interface is only available for H-Tile devices. |
| Removed the signal xcvr_reconfig_readdatavalid from the list of Hard IP Reconfiguration signals of the Intel® Stratix® 10 Avalon® -ST IP for PCI Express* . |
Since the xcvr_reconfig_readdata[31:0] bus will be valid on the third cycle after the assertion of xcvr_reconfig_read, the xcvr_reconfig_readdatavalid signal is not needed. |
| Added a description of the behavior of the Intel® Stratix® 10 Avalon® -ST IP for PCI Express* when memory read accesses are made to a disabled Expansion ROM BAR. |
If an Expansion ROM BAR is disabled, memory read accesses to that BAR are responded to with 32'h0000_0000 indicating that the BAR does not exist. |
| Raised the device support level for the Intel® Stratix® 10 Avalon® -MM Hard IP+ from Advance to Preliminary. |
Preliminary support level indicates that the IP core has been verified with preliminary timing models and also meets all functional requirements. |