L/H-Tile Hard IP for PCI Express* IP Core Release Notes

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ID 683412
Date 10/27/2023
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1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes x
1.1. L/H-Tile Hard IP for PCI Express* IP Cores for 23.2 1.2. L/H-Tile Hard IP for PCI Express* IP Cores for 23.1 1.3. L/H-Tile Hard IP for PCI Express* IP Cores for 21.4 1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 1.5. L/H-Tile Hard IP for PCI Express IP Core v20.4 1.6. L/H-Tile Hard IP for PCI Express* IP Core v19.3 1.7. L/H-Tile Hard IP for PCI Express* IP Core v19.1 1.8. L/H-Tile Hard IP for PCI Express* IP Core v18.1.1 1.9. L/H-Tile Hard IP for PCI Express* IP Core v18.0 1.10. L/H-Tile Hard IP for PCI Express* IP Core v17.1
1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 x
1.4.1. L/H-Tile Avalon® Streaming Hard IP for PCI Express* IP Core v23.0.0 1.4.2. L/H-Tile Avalon® Memory-mapped Hard IP for PCI Express* IP Core v22.2.0
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes

1.8. L/H-Tile Hard IP for PCI Express* IP Core v18.1.1

Table 9.  18.1.1 December 2018
Description Impact
Added the Link Inspector Avalon-MM Interface to the Avalon® -ST, Avalon® -MM and Avalon® -MM Hard IP+ for PCI Express* IPs. This interface allows you to access low-level link status information from the PCIe Hard IP, XCVR or PLL blocks via the Link Inspector without using the System Console.
Added the completion timeout checking feature to the Avalon® -MM Hard IP+ for PCI Express* IP. This new option in the GUI (under the Avalon® -MM Settings tab) allows you to receive a completion timeout error indicator on either the rddm_tx_data_o[15] port (if the Read Data Mover issued a Read operation to the host) or the bas_response_o[1:0] ports (if the Bursting Avalon® Slave forwarded a Read operation to the host).
Added the feature to trigger MSI interrupts via the rxm_irq_i ports to the Avalon® -MM for PCI Express* IP. This feature allows the IP core to convert a rising edge on one of the rxm_irq_i ports to an MSI interrupt and send it to the Root Port.
Note: the rxm_irq_i ports are not available when the IP core is operating in DMA mode.
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