L/H-Tile Hard IP for PCI Express* IP Core Release Notes

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ID 683412
Date 10/27/2023
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1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes x
1.1. L/H-Tile Hard IP for PCI Express* IP Cores for 23.2 1.2. L/H-Tile Hard IP for PCI Express* IP Cores for 23.1 1.3. L/H-Tile Hard IP for PCI Express* IP Cores for 21.4 1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 1.5. L/H-Tile Hard IP for PCI Express IP Core v20.4 1.6. L/H-Tile Hard IP for PCI Express* IP Core v19.3 1.7. L/H-Tile Hard IP for PCI Express* IP Core v19.1 1.8. L/H-Tile Hard IP for PCI Express* IP Core v18.1.1 1.9. L/H-Tile Hard IP for PCI Express* IP Core v18.0 1.10. L/H-Tile Hard IP for PCI Express* IP Core v17.1
1.4. L/H-Tile Hard IP for PCI Express* IP Cores for 21.3 x
1.4.1. L/H-Tile Avalon® Streaming Hard IP for PCI Express* IP Core v23.0.0 1.4.2. L/H-Tile Avalon® Memory-mapped Hard IP for PCI Express* IP Core v22.2.0
1. L/H-Tile Hard IP for PCI Express* IP Core Release Notes

1.7. L/H-Tile Hard IP for PCI Express* IP Core v19.1

Table 8.  19.1 March 2019
Description Impact
Added a chapter on the programming model for Root Ports to the Intel® Stratix® 10 Avalon® -MM Interface for PCI Express* Solutions User Guide. Added the programming model for Root Ports to help users enable Root Ports. The model:
  • Explains the Avalon® -MM CRA interface registers.
  • Explains sending and receiving TLPs through the CRA interface.
  • Shows an example of BAR0 initialization.
Removed the note stating that Root Port mode is not recommended from the Intel® Stratix® 10 Avalon® -MM and Intel® Stratix® 10 Avalon® -ST for PCI Express* Solutions User Guides. Root Port mode is fully supported in this release for both Avalon® -MM and Avalon® -ST IPs.
Removed the BIOS Enumeration Issue section from the Troubleshooting chapter of all Intel® Stratix® 10 PCI Express* User Guides. Since Intel® Stratix® 10 devices support the autonomous Hard IP feature, they can be recognized by the OS/BIOS during enumeration without having to be fully programmed.
Added the note stating that the bam_response_i[1:0] inputs should be driven to 0 to the Intel® Stratix® 10 Avalon® -MM Hard IP+ for PCI Express* User Guide. Clarified that these inputs are reserved; hence, they should be driven to 0.
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