Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.18. Revision History

Date Version Changes
April 2019 2019.04.18
  • Fixed typos.
  • Fixed two broken links.
  • Added taxonomy terms.
  • Altered the document title.
May 2017 2017.05.08

Removed support for Intel® Arria® 10 devices. For Intel® Arria® 10 support refer to the Partial Reconfiguration Solutions IP User Guide

Oct 2016 2016.10.31

Added support for Intel® Arria® 10 devices.

  • Updated content for Clock-to-Data Ratio.
  • Updated the Parameters and Ports.
  • Updated Compression instructions for standard and enhanced compression.
  • Added supporting content on using PR with JTAG.
  • Minor edits and fixed typos
May 2016 2016.05.02 Minor changes:
  • Fixed a link to the Designing for Partial Reconfiguration chapter in Vol 1 of the Intel® Quartus® Prime Handbook.
  • Fixed typos.
Nov 2015 2015.11.20 Revised the following topics:
  • Partial Reconfiguration IP Core Parameters—updated supported data width
  • Partial Reconfiguration IP Core Timing Specification—revised the timing diagram
  • Deprecated the Sample Partial Reconfiguration IP Core as an External Host on the Same Device topic
  • Added Enable Enhanced Compression topic
May 2015 2015.05.04 Revised the following topics:
  • Partial Reconfiguration IP Core Parameters—added new parameters for device family support
  • Partial Reconfiguration IP Core Ports—added new port options
  • Partial Reconfiguration IP Core Timing Specification—revised the timing diagram
January 2015 2015.01.29 Minor error corrections.
August 2014 2014.08.20

  • Added Avalon Memory Map slave interface

  • Updated Ports and Parameters to support Avalon Memory Map slave interface

  • Added Bitstream compatibility checking

  • Added sample pseudo-code for creating a freeze wrapper for multiple PR regions and creating an external host on the same device.

November 2013 2013.11.04 Initial release
Level Two Title