Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing

The Avalon® -MM interface supports read and write transfers with a slave-controlled waitrequest. You can cause the slave to stall the interconnect for as many cycles as required by asserting the waitrequest signal. If a slave uses waitrequest for either read or write transfers, it must use waitrequest for both.

A slave typically receives address, read or write, and writedata after the rising edge of the clock. A slave asserts waitrequest before the rising clock edge to hold off transfers. When the slave asserts waitrequest, the transfer is delayed. The address and control signals are held constant. Transfers complete on the rising edge of the first clk after the slave port deasserts waitrequest.

Figure 8. Read and Write Transfers for Avalon® -MM Slave Interface

The numbers in this timing diagram, mark the following transitions:

  1. address and read are asserted after the rising edge of clk. waitrequest is asserted stalling the transfer.
  2. waitrequest is sampled. Because waitrequest is asserted, the cycle becomes a wait-state. address, read, and write remain constant.
  3. The slave presents valid readdata and deasserts waitrequest.
  4. readdata and deasserted waitrequest are sampled, completing the transfer.
  5. address, writedata, and write signals are asserted. The slave responds by asserting waitrequest stalling the transfer.
  6. Deassert the waitrequest.
  7. The slave captures writedata and ends the transfer.
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