Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.13. Freeze Logic for 28-nm PR Regions

When partially reconfiguring a design, freeze all the outputs of each PR region to a known constant value.

Freezing prevents the signal receivers in the static region from receiving undefined signals during the partial reconfiguration process. Freezing is important for control signals that you drive from the PR region. Cyclone® V or Stratix® V devices require that you freeze global and non-global inputs of a PR region.

Figure 9. Freezing at PR Region Boundary
The Partial Reconfiguration IP core includes a freeze port for a single freeze signal that corresponds to the device you configure. When instantiating the IP core in your design, combine this freeze port with your system-level PR control logic to freeze the PR region output. If your design has multiple PR regions, create a decoding logic to route that freeze signal to the appropriate PR region’s freeze logic. Do not route the freeze signal to the PR regions unaffected by the current partial reconfiguration.
Note: If you are not using the Partial Reconfiguration IP core in your design, include logic to generate the freeze signal that you use for freezing the PR region outputs.

The static region logic must be independent of all the outputs from the PR regions for a continuous operation. Control the outputs of the PR regions by creating an RTL wrapper around the PR region.

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