Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

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ID 683308
Date 4/01/2024
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Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) v2.0.0
Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.4 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.3 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.1.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.2.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.0 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Update 1 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Low Latency Ethernet 10G MAC IP Core v17.0 Low Latency Ethernet 10G MAC IP Core v16.1 Low Latency Ethernet 10G MAC IP Core v16.0 Low Latency Ethernet 10G MAC IP Core v15.1 Low Latency Ethernet 10G MAC IP Core v15.0 Low Latency Ethernet 10G MAC IP Core v14.1 Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v14.0 Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v13.1
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes

Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.4

Table 2.  v22.0.4 2023.12.04
Quartus® Prime Version Description Impact
23.4 Change in the Clock Controller frequency port for 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Stratix® 10 devices. In the Clock Controller application, you must set 125MHz frequency to U5, OUT 5 and U5, OUT 8 ports instead of U5, OUT 0 and U5, OUT 8 ports.
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