Intel® Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Intel® Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. Intel® MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Intel® Stratix® 10 SoC Device Overview 4.4. Intel® MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card IO48 NAND Flash Feature Summary Block Diagram IO48 Interface Connector to Motherboard 10/100/1000 Mbps Ethernet PHY UART NAND Flash eMMC I2C GPIO HPS Clock Power Reset 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4 ) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.8.2. HPS IO-48 NAND Flash Daughter Card

Figure 14. HPS IO-48 NAND Flash Daughter Card Picture

IO48 NAND Flash Feature Summary

Table 33.  Feature Summary
Feature Name Description
IO48 Connector
  • Samtec QTH-030 Series 60-pin connector on IO48 daughter card side
  • Samtec QSH-030 Series 60-pin connector on motherboard
10/100/1000 Mbps Ethernet PHY with RGMII interface
  • Microchip KSZ9031RNX Ethernet PHY
  • RGMII MAC Interface
  • MDC/MDIO Management Interface
  • Standard RJ-45 with integrated Ethernet Transformer
UART
  • FTDI FT232R UART USB Convertor
  • Standard USB Mini-B Receptacle
NAND Flash
  • Micron MT29F8G16ADBDAH4-AIT:D
  • 1.8V 8 Gb SLC ASYNC NAND Flash
  • x16 bit data width
  • VFBGA-63 Package
  • Multiplexed with eMMC Flash with resistor MUX (Cannot use simultaneously)
eMMC
  • Micron MTFC8GAKAJCN-4M IT
  • 8 GB 5.0 compliant eMMC
  • Not support eMMC data strobe due to Intel® Stratix® 10 HPS limitation
  • VPFBGA-153 Package
I2C
  • HPS I2C and FPGA I2C is connected together on the motherboard
GPIO
  • 2 GPIOs as Push Buttons
  • 3 GPIOs as LEDs
  • 1 GPIO as Ethernet Interrupt from Ethernet PHY
HPS Clock
  • 1 On-board 25 MHz oscillator provides HPS clock
Mechanical
  • Supposed 3" x 1.8" board size

Block Diagram

Figure 15. NAND Daughter Card Block Diagram

IO48 Interface

Stratix 10 SoC IO48 bank can be multiplexed to different peripheral interfaces. On NAND daughter card, IO48 bank is interfaced with Ethernet RGMII, UART, I2C, NAND Flash, eMMC and GPIO interfaces.

Table 34.  IO48 Pinout MUX
HPS Pin Name Peripheral Name Signal
Q1_1 NAND ADQ0
Q1_2 NAND ADQ1
Q1_3 NAND WE_N
Q1_4 NAND RE_N
Q1_5 NAND WP_N
Q1_6 NAND ADQ2
Q1_7 NAND ADQ3
Q1_8 NAND CLE
Q1_9 NAND ADQ4
Q1_10 NAND ADQ5
Q1_11 NAND ADQ6
Q1_12 NAND ADQ7
Q2_1 NAND ALE
Q2_2 NAND RB
Q2_3 NAND CE_N
Q2_4 CM HPS_OSC_CLK
Q2_5 NAND ADQ8
Q2_6 NAND ADQ9
Q2_7 NAND ADQ10
Q2_8 NAND ADQ11
Q2_9 NAND ADQ12
Q2_10 NAND ADQ13
Q2_11 NAND ADQ14
Q2_12 NAND ADQ15
Q3_1 GPIO1 IO0
Q3_2 GPIO1 IO1
Q3_3 UART0 TX
Q3_4 UART0 RX
Q3_5 GPIO1 IO4
Q3_6 GPIO1 IO5
Q3_7 I2C1 SDA
Q3_8 I2C1 SCL
Q3_9 MDIO2 MDIO
Q3_10 MDIO2 MDC
Q3_11 GPIO1 IO10
Q3_12 GPIO1 IO11
Q4_1 EMAC2 TX_CLK
Q4_2 EMAC2 TX_CTL
Q4_3 EMAC2 RX_CLK
Q4_4 EMAC2 RX_CTL
Q4_5 EMAC2 TXD0
Q4_6 EMAC2 TXD1
Q4_7 EMAC2 RXD0
Q4_8 EMAC2 RXD1
Q4_9 EMAC2 TXD2
Q4_10 EMAC2 TXD3
Q4_11 EMAC2 RXD2
Q4_12 EMAC2 RXD3

Connector to Motherboard

To connect between motherboard and IO48 NAND Flash daughter card, Samtec QSH/QTH series connectors are applied. Samtec QTH-030 60-pin connector is used on IO48 NAND Flash daughter card side while Samtec QSH 60-pin is at the motherboard side.

10/100/1000 Mbps Ethernet PHY

This daughter card supports copper RJ-45 10/100/1000 Mbps Ethernet using an external Ethernet PHY Microchip KSZ9031RNX. The PHY-to-MAC interface employs RGMII using Intel® Stratix® 10 SoC IO48 EMAC2 to transmit and receive data. For management interface, it uses MDC/MDIO interface between EMAC2 and Ethernet PHY.

Figure 16. Ethernet PHY Block Diagram
Table 35.  Ethernet Signals List
Net Name IO48 Location Type Description
ENET_TXD0 Q4_5 IN RGMII Data Transmit Bit 0
ENET_TXD1 Q4_6 IN RGMII Data Transmit Bit 1
ENET_TXD2 Q4_9 IN RGMII Data Transmit Bit 2
ENET_TXD3 Q4_10 IN RGMII Data Transmit Bit 3
ENET_GTX_CLK Q4_1 IN RGMII Transmit Reference Clock
ENET_TX_EN Q4_2 IN RGMII Transmit Control (TX_CTL)
ENET_RXD0 Q4_7 OUT RGMII Data Receive Bit 0
ENET_RXD1 Q4_8 OUT RGMII Data Receive Bit 1
ENET_RXD2 Q4_11 OUT RGMII Data Receive Bit 2
ENET_RXD3 Q4_12 OUT RGMII Data Receive Bit 3
ENET_RX_CLK Q4_3 OUT RGMII Receive Reference Clock
ENET_RX_DV Q4_4 OUT RGMII Receive Control (RX_CTL)
ENET_MDC Q3_10 IN Management Clock
ENET_MDIO Q3_9 INOUT Management Data
ENET_INTn Q3_1 OUT Ethernet PHY Interrupt Output

UART

Table 36.  UART Signals List
Net Name IO48 Location Type Description
UART_TX Q3_3 IN UART TX from Intel® Stratix® 10 HPS to FT232R
UART_RX Q3_4 OUT UART RX from FT232R to Intel® Stratix® 10 HPS
UART_RESETn   IN FT232R reset input connected to HPS_RESETn

Based on the signal direction, HPS IO48's UART_TX is connected to FT232R's RXD pin and HPS IO48's UART_RX is connected to FT232R's TXD.

Figure 17. UART Connection

NAND Flash

The IO48 NAND flash daughter card supports a 16-bit NAND flash. Since some NAND flash pins are multiplexed with eMMC pins, NAND flash and eMMC flash cannot be used simultaneously. There are MUX resistors to select related IO48 signals are connected to NAND flash or eMMC flash. The default setup is NAND flash.

The proposed NAND flash memory is MT29F8G16ADBDAH4-AIT:D manufactured by Micron. Major parameters are as listed below:
Table 37.  NAND Flash Memory Parameters
Paramater Description
Type SLC NAND
Density 8 Gb
Data Width 16-bit
Voltage 1.8 V
Package VFBGA-63
Operational Temperature -40 C to +85 C

An optional NAND socket can be used for easy NAND Flash replacement when NAND flash is not soldered down. The socket vendor is Ironwood with part number SG-BGA-6367.

Table 38.  NAND Flash Memory Signal List
Net Name IO48 Location Type Direction
NAND_ADQ0 Q1_1 INOUT Bidirectional data bit 0
NAND_ADQ1 Q1_2 INOUT Bidirectional data bit 1
NAND_ADQ2 Q1_6 INOUT Bidirectional data bit 2
NAND_ADQ3 Q1_7 INOUT Bidirectional data bit 3
NAND_ADQ4 Q1_9 INOUT Bidirectional data bit 4
NAND_ADQ5 Q1_10 INOUT Bidirectional data bit 5
NAND_ADQ6 Q1_11 INOUT Bidirectional data bit 6
NAND_ADQ7 Q1_12 INOUT Bidirectional data bit 7
NAND_ADQ8 Q2_5 INOUT Bidirectional data bit 8
NAND_ADQ9 Q2_6 INOUT Bidirectional data bit 9
NAND_ADQ10 Q2_7 INOUT Bidirectional data bit 10
NAND_ADQ11 Q2_8 INOUT Bidirectional data bit 11
NAND_ADQ12 Q2_9 INOUT Bidirectional data bit 12
NAND_ADQ13 Q2_10 INOUT Bidirectional data bit 13
NAND_ADQ14 Q2_11 INOUT Bidirectional data bit 14
NAND_ADQ15 Q2_12 INOUT Bidirectional data bit 15
NAND_WEn Q1_3 IN Write Enable
NAND_REn Q1_4 IN Read Enable
NAND_WPn Q1_5 IN Write Protect
NAND_CLE Q1_8 IN Command Latch Enable
NAND_ALE Q2_1 IN Address Latch Enable
NAND_RBn Q2_2 OUT Ready/Busy
NAND_CEn Q2_3 IN Chip Enable

eMMC

The IO48 NAND flash daughter card also supports a 8-bit eMMC flash. Since the eMMC flash pins are multiplexed with NAND pins, NAND Flash and eMMC Flash cannot be used simultaneously. There are MUX resistors to select related IO48 signals are connected to NAND flash or eMMC flash. The default setup is NAND flash, not eMMC.

The proposed eMMC flash memory is MTFC8GAKAJCN-4M IT manufactured by Micron.
Table 39.  eMMC Flash Parameters
Parameter Description
Type eMMC with 5.0-compliant (JESD84-B50)
Density 8 GB
Data Width 8-bit
Voltage 3.3 V VCC and 1.8 V/3.3 V VCCQ operation (VCCQ=1.8 V on this card)
Package VFBGA-153
Operational Temperature -40 C to +85 C
Table 40.  eMMC Signal List
Net Name IO48 Location Type Description
EMMC_D0 Q1_3 INOUT eMMC bidirectional data bus bit
EMMC_D1 Q1_4 INOUT eMMC bidirectional data bus bit
EMMC_D2 Q1_5 INOUT eMMC bidirectional data bus bit
EMMC_D3 Q1_6 INOUT eMMC bidirectional data bus bit
EMMC_D4 Q1_7 INOUT eMMC bidirectional data bus bit
EMMC_D5 Q1_8 INOUT eMMC bidirectional data bus bit
EMMC_D6 Q1_9 INOUT eMMC bidirectional data bus bit
EMMC_D7 Q1_10 INOUT eMMC bidirectional data bus bit
EMMC_CLK Q1_1 IN eMMC clock input
EMMC_CMD Q1_2 INOUT eMMC bi-directional command
EMMC_DS   OUT eMMC Data Strobe. No Connection. Intel® Stratix® 10 does not support it.
EMMC_RSTn   IN eMMC reset input. Connected to HPS_RESETn.
Note: Since Intel® Stratix® 10 HPS does not support HS400, Data Strobe pin on eMMC flash is not used. HS400 is not supported on this board.

I2C

The FPGA I2C and HPS I2C are connected together on motherboard. HPS I2C left floating on this IO48 debug daughter card although is connected to IO48 connector. A 3-pin 2.54 mm header is reserved with HPS I2C.

GPIO

Table 41.  IO48 GPIO Signals List
Net Name IO48 Location Type Description
HPS_PB0 Q3_5 OUT Push Button 0 on daughter card
HPS_PB1 Q3_6 OUT Push Button 1 on daughter card
HPS_LED0 Q3_2 IN LED 0 on daughter card active high
HPS_LED1 Q3_11 IN LED 1 on daughter card active high
HPS_LED2 Q3_12 IN LED 2 on daughter card active high
ENET_INTn Q3_1 OUT Ethernet PHY interrupt output

HPS Clock

One on-board oscillator provides a fixed 25 MHz single-ended clock for HPS PLL input.

Figure 18. Clock Diagram

Power

There are two power rails drawn from motherboard through Samtec connector VCC_12V and VCCIO_HPS. VCC_12V is major power source and it is converted to other power rails with on-board regulators. It is recommended to have at least 1 A capability on VCC_12V power rail.

VCCIO_HPS is HPS I/O buffers power supply from motherboard.

Figure 19. Power Diagram

Reset

Reset is from MAX 10 CPLD on Stratix 10 SoC motherboard. The MAX 10 controls all devices' resets on the development kit.

Figure 20. Reset Diagram
Level Two Title