AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

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ID 683185
Date 6/09/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup 1.4. Hardware Checkout Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices 1.9. Appendix
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment 1.4.1.2. Extended Multiblock Alignment
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

1.4.2. Receiver Transport Layer

To check the data integrity of the payload data stream through the receiver (RX) JESD204C Intel® FPGA IP and transport layer, the ADC is configured to output short and long transport layer test patterns and ramp test pattern. The ADC is also set to operate with the same configuration as set in the JESD204C Intel® FPGA IP. The short and long transport layer test patterns and ramp test pattern (as defined in section 6.6 of the JESD204C specification and the Short and Long Transport Test Mode and Ramp Test Mode sections in the ADC12DJ5200RF data sheet) are observed at the data output of the RX transport layer. The ramp checker in the FPGA fabric checks ramp data integrity for one minute. For short and long transport layer test pattern, approximately 8k frame clock cycle data captured by the Signal Tap logic analyzer is exported as .csv file and checked for compliance. The j204c_rx_crc_err and j204c_rx_cmd_par_err signals are monitored with raising edge trigger in the Signal Tap logic analyzer for 5 minutes, while the RX JESD204C Intel® FPGA IP register rx_err is polled continuously for zero value over 10 minutes.

Figure 3. Data Integrity Check Using Ramp Checker
Table 3.  Transport Layer Test Cases
Test Case Objective Description Passing Criteria
TL.1 Check the transport layer mapping of the data channel using short transport layer test pattern. The following signals in <ip_variant_name> _base.v are tapped:
  • j204c_rx_avst_ready
  • j204c_rx_avst_valid
  • j204c_rx_avst_data

    [(M*S*WIDTH_MULP*N)-1:0] 3

  • j204c_rx_avst_control [(M*S*WIDTH_MULP*CS)-1:0] 4 5 6

    The rxframe_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_avst_valid is asserted.
  • The j204c_rx_avst_ready is asserted.
  • No short transport layer test pattern is mismatched.
TL.2 Check the transport layer mapping of the data channel using long transport layer test pattern. The following signals in <ip_variant_name> _base.v are tapped:
  • j204c_rx_avst_ready
  • j204c_rx_avst_valid
  • j204c_rx_avst_data

    [(M*S*WIDTH_MULP*N)-1:0] 3 4 5 6

  • j204c_rx_avst_control

    [(M*S*WIDTH_MULP*CS)-1:0] 3 4 5 7

    The rxframe_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_avst_valid is asserted.
  • The j204c_rx_avst_ready is asserted.
  • No long transport layer test pattern is mismatched.
TL.3 Check the transport layer mapping of the data channel using ramp test pattern.
  • j204c_rx_avst_ready
  • j204c_rx_avst_valid
  • j204c_rx_avst_data

    [(M*S*WIDTH_MULP*N)-1:0] 3 4 5 6

  • j204c_rx_avst_control

    [(M*S*WIDTH_MULP*CS)-1:0] 3 4 5 7

    The rxframe_clk is used as the sampling clock for the Signal Tap.

  • rx_patchk_data_error_int

    The rxframe_clk is used as the sampling clock for the Signal Tap.

    The rx_patchk_data_error_int signal indicates a pass or fail for the ramp checker.

  • The j204c_rx_avst_valid is asserted.
  • The j204c_rx_avst_ready is asserted.
  • The rx_patchk_data_error_in signals is deasserted.
Related Information
3 M is the number of converters.
4 S is the number of transmitted samples per converter per frame.
5 WIDTH_MULP is the data width multiplier between the application layer and transport layer.
6 N is the number of conversion bits per converter.
7 CS is the number of control bits per conversion samples
Level Two Title