AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

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ID 683185
Date 6/09/2020
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup 1.4. Hardware Checkout Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices 1.9. Appendix
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment 1.4.1.2. Extended Multiblock Alignment
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

1.1. Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

  • Intel® Stratix® 10 TX Signal Integrity (SI) Development Kit (Production Rev B Edition) (1ST280EY2F55E1VG) with 12 V power adaptor
  • TI ADC12DJ5200RF EVM with 5 V power adaptor
  • SMA (Male) to SMP (Female) cables
  • USB type A to B cable
  • Mini-USB cable
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