Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

Transceiver Performance for Intel® Stratix® 10 H-Tile Devices

Table 57.   Intel® Stratix® 10 H-Tile Transmitter and Receiver Datarate Performance
Symbol Description Transceiver Speed Grade
-1 -2 -3
GX channels Chip-to-chip and Backplane 17.4 Gbps
GXT channels Chip-to-chip and Backplane 28.3 Gbps 94 26.6 Gbps N/A
Note: Refer to the Transceiver Power Supply Operating Conditions for VCCR_GXB and VCCT_GXB specifications when using bonded and non-bonded transceiver channels in Intel® Stratix® 10 H-Tile devices.
Table 58.  H-Tile ATX PLL Performance
Symbol/Description Condition Transceiver Speed Grade 1 Transceiver Speed Grade 2 Transceiver Speed Grade 3 Unit
Supported Output Frequency Maximum Frequency 14.15 13.3 8.7 GHz
Minimum Frequency 500 MHz
tLOCK 95 Maximum Frequency 1 ms
tARESET 96 — 25 Avalon Clock Cycles
Note: TX jitter specifications for the SerialLite III protocol at 17.4 Gbps are as low as: TJ = 0.32 UI, RJ = 0.15 UI, DJ = 0.18 UI, and DCD = 0.05 UI.
Table 59.  H-Tile Fractional PLL Performance
Symbol/Description Condition Mode All Transceiver Speed Grades Unit
Supported Output Frequency (VCO frequency based) Maximum datarate Transceiver - HDMI 12.5 Gbps
Transceiver - General 12.5
Transceiver - OTN, SDI Cascade 14.025
Minimum datarate Transceiver - HDMI 4.6 Gbps
Transceiver - General 6
Transceiver - OTN, SDI Cascade 7
tLOCK 95 Maximum Frequency   1 ms
tARESET 96 —   25 Avalon Clock Cycles
Table 60.  H-Tile CMU PLL Performance
Symbol/Description Condition All Transceiver Speed Grades Unit
Supported Output Frequency Maximum Frequency 5.15625 GHz
Minimum Frequency 2.450 GHz
tLOCK 95 Maximum Frequency 1 ms
tARESET 96 — 25 Avalon Clock Cycles
94 Only four GXT channels per bank are supported for backplane applications operating at 28.3 Gbps.
95 This specification applies after the ATX PLL, fPLL, or CMU PLL has completed calibration.
96 You must use the Avalon-MM interface to hold the PLLs in reset for the specified cycles by writing to the ATX PLL, fPLL, or CMU PLL pll_powerdown register.
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