Reed-Solomon II IP Core User Guide

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ID 683144
Date 11/17/2015
Public
Document Table of Contents
Document Table of Contents x
1. About the Reed-Solomon II IP Core 2. Reed-Solomon II IP Core Getting Started 3. Reed-Solomon II IP Core Functional Description 4. Document Revision History
1. About the Reed-Solomon II IP Core x
1.1. Altera DSP IP Core Features 1.2. Reed-Solomon II IP Core Features 1.3. DSP IP Core Device Family Support 1.4. DSP IP Core Verification 1.5. Reed-Solomon II IP Core Release Information 1.6. Reed-Solomon II IP Core Performance and Resource Utilization
2. Reed-Solomon II IP Core Getting Started x
2.1. Licensing IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores 2.4. Simulating Altera IP Cores in other EDA Tools 2.5. DSP Builder Design Flow
2.1. Licensing IP Cores x
2.1.1. OpenCore Plus IP Evaluation 2.1.2. Reed-Solomon II IP Core OpenCore Plus Timeout Behavior
2.3. Generating IP Cores x
2.3.1. Files Generated for Altera IP Cores and Qsys Systems
3. Reed-Solomon II IP Core Functional Description x
3.1. Architecture 3.2. Reed-Solomon II IP Core Parameters 3.3. Reed-Solomon II IP Core Interfaces and Signals
3.1. Architecture x
3.1.1. Reed-Solomon II Encoder 3.1.2. Reed-Solomon II Decoder 3.1.3. Multiple Input Channels
3.3. Reed-Solomon II IP Core Interfaces and Signals x
3.3.1. Avalon-ST Interfaces in DSP IP Cores 3.3.2. Reed-Solomon II IP Core Signals
1. About the Reed-Solomon II IP Core
2. Reed-Solomon II IP Core Getting Started
3. Reed-Solomon II IP Core Functional Description
4. Document Revision History

3.3.2. Reed-Solomon II IP Core Signals

Table 7.  Clock and Reset Signals
Name Avalon-ST Type Direction Description
clk_clk clk Input The main system clock. The whole IP core operates on the rising edge of clk_clk .
reset_reset_n reset_n Input An active low signal that resets the entire system when asserted. You can assert this signal asynchronously. However, you must deassert it synchronous to the clk_clk signal. When the IP core recovers from reset, ensure that the data it receives is a complete packet.
Table 8.   Avalon-ST Input and Output Interface Signals
Name Avalon-ST Type Direction Description
in_ready ready Output Data transfer ready signal to indicate that the sink is ready to accept data. The sink interface drives the in_ready signal to control the flow of data across the interface. The sink interface captures the data interface signals on the current clk rising edge.
in_valid valid Input Data valid signal to indicate the validity of the data signals. When you assert the in_valid signal, the Avalon-ST data interface signals are valid. When you deassert the in_valid signal, the Avalon-ST data interface signals are invalid and must be disregarded. You can assert the in_valid signal whenever data is available. However, the sink only captures the data from the source when the IP core asserts the in_ready signal.
in_data[] data Input Data input for each codeword, symbol by symbol. Valid only when you assert the in_valid signal. For Qsys systems, the in_data bus is: [in_numn,in_numcheck,data] If you have no variable check it is: [numn,data]

For example, for a maximum codeword length of 255 corresponding to 8 bits:

  • in_data[7:0] = data
  • in_data[15:0] = numn
in_channel channel Input Specifies the channel number for data the IP core transfers on the current cycle. The in_channel signal is available only when you configure the IP core to support multiple channels.
in_startofpacket sop Input Start of packet (codeword) signal.
in_endofpacket eop Input End of packet (codeword) signal.
in_error error Input Error signal. Specifies if the input data symbol is an error and whether the decoder can consider it as an erasure. Erasures-supporting decoders only.
out_startofpacket sop Output Start of packet (codeword) signal. This signal indicates the codeword boundaries on the in_data[] bus. When the IP core drives this signal high, it indicates that the start of packet is present on the in_data[] bus. The IP core asserts this signal on the first transfer of every codeword.
out_endofpacket eop Output End of packet (codeword) signal. This signal indicates the packet boundaries on the in_data[] bus. When the IP core drives this signal high, it indicates that the end of packet is present on the in_data[] bus. The IP core asserts this signal on the last transfer of every packet.
out_ready ready Input Data transfer ready signal to indicate that the downstream module is ready to accept data. The source provides new data (if available) when you assert the out_ready signal and stops providing new data when you deassert the out_ready signal. If the source is unable to provide new data, it deasserts out_valid for one or more clock cycles until it is prepared to drive valid data interface signals.
out_valid valid Output Data valid signal. The IP core asserts the out_valid signal high, whenever a valid output is on out_data ; the IP core deasserts the signal when there is no valid output on out_data .
out_data data Output Contains decoded output when the IP core asserts the out_valid signal. The corrected symbols are in the same order that they are entered.
out_channel channel Output Specifies the channel whose result is presented at out_data . Available only when you configure the IP core to support multiple channels.
out_error error Output Indicates non-correctable codeword (decoder only). Valid when the IP core asserts out_endofpacket .
Table 9.   Configuation Signals
Name Direction Description
num_check Output Sets the variable number of check symbols up to a maximum value set by the parameter R (variable option only).
numn Output Variable value of N. Can be any value from the minimum allowable value of N up to the selected value of N (variable and erasures-supporting option only).
Table 10.   Status Interface Signals
Name Avalon-ST Type Direction Description
status_error_value conduit Output Error correction value for every valid data symbol.
status_num_error_symbol conduit Output Number of error symbols in a codeword. This signal is valid when the IP core asserts out_endofpacket . Only available when you turn on Error symbol count .
status_num_error_bit conduit Output Number of error bits in a codeword. This signal is valid when the IP core asserts the out_endofpacket . Only available when you turn on Error bit count and select Full for Error bits count format .
status_num_error_bit0 conduit Output Number of bit errors for the correction from bit 1 to bit 0. The latest is the correct bit. This signal is valid when the IP core asserts the out_endofpacket . Only available when you turn on Error bit count and select Split for Error bits count format .
status_num_error_bit0 conduit Output Number of bit errors for the correction from bit 0 to bit 1. The latest is the correct bit. This signal is valid when the IP core asserts the out_endofpacket . Only available when you turn on Error bit count and select Split for Error bits count format .
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