Visible to Intel only — GUID: hco1421698027247
Ixiasoft
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) Release Notes ( Agilex™ 7 M-Series Devices)
PHY Lite for Parallel Interfaces Intel® FPGA IP (altera_phylite_s20) Release Notes ( Agilex™ 7 F-Series and I-Series Devices)
PHY Lite for Parallel Interfaces Intel FPGA IP Core v19.3.0
PHY Lite for Parallel Interfaces Intel FPGA IP Core v18.1
PHY Lite for Parallel Interfaces Intel FPGA IP Core v18.0
Intel FPGA PHYLite for Parallel Interfaces IP Core v17.1
Altera PHYLite for Parallel Interfaces IP Core v16.0
Altera PHYLite for Parallel Interfaces IP Core v15.1
Altera PHYLite for Memory IP Core v14.1
Altera PHYLite for Memory IP Core v14.0 Arria 10 Edition
PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v5.0.0
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v4.1.0
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v4.0.0
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v3.0.0
PHY Lite for Parallel Interfaces Intel® FPGA IP (phylite_ph2) v2.0.0
PHY Lite for Parallel Interfaces Intel Agilex FPGA IP (altera_phylite_s20) v22.3.0
PHY Lite for Parallel Interfaces Intel Agilex FPGA IP (altera_phylite_s20) v22.1.0
PHY Lite for Parallel Interfaces Intel Agilex FPGA IP (altera_phylite_s20) v21.0.0
PHY Lite for Parallel Interfaces Intel Agilex FPGA IP (altera_phylite_s20) v20.3.0
Visible to Intel only — GUID: hco1421698027247
Ixiasoft
Altera PHYLite for Memory IP Core v14.0 Arria 10 Edition
| Description | Impact |
|---|---|
| Added dynamic reconfiguration | - |
| Added I/O standard and OCT settings | - |
| Added complementary strobe type | - |
| Changed pll_locked port name to interface_locked | - |