AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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ID 683049
Date 12/19/2017
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Link Up Test Results

Figure 8. Successful Link Up Indicated in the System ConsoleThis figure illustrates the expected output from the Tcl Console of the System Console if the link up is successful.

When the link up is successful, you should observe the following conditions:

  • USER_LED0–USER_LED3 (D12–D15) illuminate
  • USER_LED4 (D16) turned off
Figure 9. On-board User LEDs
Table 2.  On-board User LEDs Indication
On-board User LED Signal Indication when LED Illuminates
LED D12 rx_frame_rst_n The transport layers and test pattern checkers are out of reset.
LED D13 rx_link_rst_n The IP cores, transport layers, and deterministic latency module are out of reset.
LED D14 alldev_lane_aligned All lanes are aligned for two JESD204B IP cores receiver.
LED D15 rx_dev_sync_n_out The receivers at link 0 and link 1 have successful received K28.5 characters.
LED D16 rx_link_error The interrupt is triggered at any of the JESD204B RX IP cores.
Level Two Title