AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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ID 683049
Date 12/19/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Compiling the Project to Include Signal Tap II File

The reference design provided does not enable Signal Tap II Logic Analyzer in the Intel® Quartus® Prime project.

To compile the design that include the Signal Tap II file (.stp) into the Intel® Quartus® Prime project, follow these steps:

  1. To test the reference design targeted for Intel® Stratix® 10 GX device, download the reference design file to your local project directory.
  2. Launch the Intel® Quartus® Prime Pro Edition software.
  3. To prepare the design template in the Intel® Quartus® Prime Pro Edition software GUI, click File > Open and change the file type to the Quartus Prime Design Template File (*.par). Browse to the <project>.par file and click Ok.
  4. Turn on Assignments > Settings > Category > Enable Signal Tap II Logic Analyzer.
  5. Browse to the stp1.stp file located at the /stp directory and click Ok.
  6. To compile the project, select Processing > Start Compilation.
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