AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Download PDF
ID 683049
Date 12/19/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Checking the Basic Operation

To check on the basic operation, follow these steps:
  1. Make sure the I/O PLL core reference clock (refclk_core), transceiver clock data recovery (CDR) reference clock (refclk_xcvr), and receiver (RX) recovered clock (rxphy_clk) are 160 MHz.
    The LMK04828 clock generator from the ADC12DJ3200 EVM module provides the reference clock to I/O PLL and transceiver CDR. A frequency checker module is added to this reference design to verify the I/O PLL core reference clock, transceiver CDR reference clock, and RX recovered clock frequency are correct. You can view the measured clock frequency in the Signal Tap II file by clicking at the freq_chk instance as indicated in the following figure. The frequency values of all measured clocks are displayed in Hz after running analysis or autorun analysis.
    Figure 6. Measured Reference Clock and Recovered Clock Frequencies
  2. Verify the RX PHY status by monitoring the status of rx_is_lockedtodata[7..0], rx_analogreset[7:0], rx_digitalreset[7:0], and rx_cal_busy[7:0] signals for link 0 and link 1.
    These signals are available under rx_phy instance in the Signal Tap II file.
    Table 1.  Bits for Each Lane for Normal Operation of the JESD204B RX Paths
    Signal Bit
    rx_is_lockedtodata 1
    rx_analogreset 0
    rx_digitalreset 0
    rx_cal_busy 0
    Figure 7. RX PHY Status
Level Two Title