1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters 5. Interface Signals 6. Configuration Registers 7. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Clocking and Reset Sequence 3.2. Timing Constraints 3.3. Operation Speed Switching 3.4. USXGMII 3.5. Fmax Requirement
3.1. Clocking and Reset Sequence x
3.1.1. Clocking 3.1.2. Reset Sequence
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

5.5. XGMII Signals

Table 19.  XGMII Signals
Signal Name Direction Width Description PHY Configurations
XGMII Transmit
xgmii_tx_control Input 4 TX control from the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration. 10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_tx_data Input 32 TX data from the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.
xgmii_tx_valid Output 1 Indicates valid data on xgmii_tx_control and xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as shown below:
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
XGMII Receive
xgmii_rx_control Output 4 RX control to the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration. 10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_rx_data Output 32 RX data to the MAC for all speeds of the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.
xgmii_rx_valid Output 1 Indicates valid data on xgmii_rx_control and xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table below.
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.
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