1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813667
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters 5. Interface Signals 6. Configuration Registers 7. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the Agilex™ 5 Reference and System PLL IP
3. Functional Description x
3.1. Clocking and Reset Sequence 3.2. Timing Constraints 3.3. Operation Speed Switching 3.4. USXGMII 3.5. Fmax Requirement
3.1. Clocking and Reset Sequence x
3.1.1. Clocking 3.1.2. Reset Sequence
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration SRC Signals
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

2.3. Specifying the IP Core Parameters and Options

The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP parameter editor allows you to quickly configure your custom IP variation.
  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or File > Open Project to open an existing Quartus® Prime project.
    The wizard prompts you to specify a device.
  2. In the IP Catalog (Tools > IP Catalog), double-click 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP to customize the IP.
    The New IP Variant window appears.
  3. Specify a top-level name for your custom IP variation.
    The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click Create.
    The parameter editor appears.
  5. Specify the parameters for your IP core variation in the parameter editor. Refer to Parameters for information about specific IP core parameters.
  6. Optionally, to generate a MAC+PHY simulation testbench or compilation and hardware design example, follow the instructions in the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 5 Devices.
  7. Click Generate HDL.
    The Generation dialog box appears.
  8. Specify output file generation options, and then click Generate.
    The IP variation files generate according to your specifications.
  9. Click Finish.
    The parameter editor adds the top-level .ip file to the current project automatically.
  10. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
Related Information
Level Two Title