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Ixiasoft
2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MII or PCS-Only Interface for FGT Transceivers
2.6. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.7. MAC Flow Control Interface
2.8. Status Interface
2.9. Avalon® Memory-Mapped Reconfiguration Interfaces
2.10. Precision Time Protocol Interface
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Ixiasoft
1. Introduction
Updated for: |
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Intel® Quartus® Prime Design Suite 22.1 |
IP Version 2.0.0 |
The F-Tile Ethernet Multirate Intel® FPGA IP core is a multirate version of the F-Tile Ethernet Intel FPGA Hard IP core that supports the dynamic reconfiguration flow in the Intel® Agilex™ devices with F-tile. The IP core provides various options to specify the power up settings, and target dynamic reconfiguration profiles for your design.