4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Getting Started with 4G Turbo-V IP 3. Designing with the 4G Turbo-V Intel® FPGA IP 4. 4G Turbo-V Intel® FPGA IP Functional Description 5. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. 4G Turbo-V IP Release Information 1.4. 4G Turbo-V Performance and Resource Utilization
2. Getting Started with 4G Turbo-V IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 4G Turbo-V IP Timeout Behavior
3. Designing with the 4G Turbo-V Intel® FPGA IP x
3.1. Generating a 4G Turbo-V IP 3.2. Simulating the IP with the RTL Simulator 3.3. Simulating a 4G Turbo-V IP with MATLAB 3.4. Simulating a 4G Turbo-V IP with C-Models
4. 4G Turbo-V Intel® FPGA IP Functional Description x
4.1. 4G Turbo-V Downlink Accelerator 4.2. 4G Turbo-V Uplink Accelerator 4.3. 4G Turbo-V Signals and Interfaces
4.1. 4G Turbo-V Downlink Accelerator x
4.1.1. Turbo Encoder 4.1.2. Rate Matcher 4.1.3. Input and Output Data Formats 4.1.4. Latency Calculations 4.1.5. Throughput Calculations
4.2. 4G Turbo-V Uplink Accelerator x
4.2.1. Turbo Decoder 4.2.2. Input and Output Data Formats 4.2.3. Latency Calculations 4.2.4. Throughput Calculations
4.3. 4G Turbo-V Signals and Interfaces x
4.3.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Getting Started with 4G Turbo-V IP
3. Designing with the 4G Turbo-V Intel® FPGA IP
4. 4G Turbo-V Intel® FPGA IP Functional Description
5. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

4.2.2. Input and Output Data Formats

Uplink accelerator data formats.
Table 11.  Input Data FormatThe uplink accelerator takes Kπ clock cycles and 3 LLRs per clock cycle, where input LLR bitwidth (WLLR ) = 8.
Input Order sink_data
3WLLR-1 down to 2WLLR 2WLLR-1 down to WLLR WLLR-1 down to 0
0 V0 (2) V0 (1) V0 (0)
1 V1 (2) V1 (1) V1 (0)
2 V2 (2) V2 (1) V2 (0)
… … … …
Kπ-1 VKπ-1 (2) VKπ-1 (1) VKπ-1 (0)
Table 12.  Input Data FormatIn deinterleaver bypass mode, the uplink accelerator takes K+4 clock cycles and 3 LLRs per clock cycle, where input LLR bitwidth (WLLR ) = 8.
Input Order sink_data
3WLLR-1 down to 2WLLR 2WLLR-1 down to WLLR WLLR-1 down to 0
0 Z’0 Z0 X0
1 Z’1 Z1 X1
… … … …
K-1 Z’K-1 ZK-1 XK-1
K XK+1 ZK XK
K+1 ZK+2 XK+2 ZK+1
K+2 X’K+1 Z’K X’K
K+3 Z’K+2 X’K+2 Z’K+1
Table 13.  Output Data FormatThe uplink accelerator outputs Wout=16 bits per clock cycle and the output block size is K
Output Order source_data
Wout down to 0
0 XWout-1, …,X2, X1,X0
1 X2Wout-1, …,XWout+2, XWout+1, XWout
… …
K/Wout-1 XK-1, …,XK-Wout+2, XK-Wout+1, XK-Wout
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