Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 4/13/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
2.1. Supported Simulators 2.2. Supported Simulation Levels 2.3. Supported Hardware Description Languages 2.4. Supported Simulation Flows 2.5. Preparing for Simulation 2.6. Running a Simulation (Custom Flow) 2.7. Intel FPGA Simulation Basics Revision History
2.5. Preparing for Simulation x
2.5.1. Compiling Simulation Model Libraries 2.5.2. Using The EDA Netlist Writer 2.5.3. Simulating Intel® FPGA IP Cores
2.5.3. Simulating Intel® FPGA IP Cores x
2.5.3.1. Generating IP Simulation Files 2.5.3.2. Scripting IP Simulation
2.5.3.2. Scripting IP Simulation x
2.5.3.2.1. Generating a Combined Simulator Setup Script 2.5.3.2.2. Incorporating Simulator Setup Scripts from the Generated Template
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support x
3.1. Quick Start Example (ModelSim with Verilog) 3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines 3.3. ModelSim Simulation Setup Script Example 3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 3.5. Unsupported Features 3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines x
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries 3.2.2. Passing Parameter Information from Verilog HDL to VHDL 3.2.3. Viewing Simulation Messages 3.2.4. Generating Signal Activity Data for Power Analysis 3.2.5. Viewing Simulation Waveforms 3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
3.2.4. Generating Signal Activity Data for Power Analysis x
3.2.4.1. Generating Standard Delay Output for Power Analysis
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History

Document Version Intel® Quartus® Prime Version Changes
2022.04.13 22.1
  • Revised name of Questa* Intel® FPGA Edition and QuestaSim for latest guidelines throughout.
2021.10.04 21.3
  • Added support for Questa* Intel® FPGA Edition simulator.
  • Removed support for ModelSim - Intel FPGA Edition simulator.
  • Updated directory names in Using Questa* Intel® FPGA Edition Precompiled Libraries topic.
  • Removed note about Maintain Hierarchy limit in Viewing Simulation Messages topic.
2021.03.29 21.1 Updated Generating Signal Activity Data for Power Analysis topic for latest behavior.
2019.06.19 19.1.0
  • Added footnote about ModelSim Remote Desktop limits to "Unsupported Features" topic.
2019.04.01 19.1.0
  • Described new support for generation of SDO for use in power analysis.
2017.11.06 17.1.0
  • Changed title to ModelSim - Intel FPGA Edition, ModelSim* , and QuestaSim Support*
  • Removed Simulating Transport Delays and Disabling Timing Violations on Registers topics. Intel® Quartus® Prime Pro Edition does not support timing simulation.
  • Added Simulation Library Compiler details and another step to Quick Start Example

Date

Version

Changes

2017.05.08 17.0.0
  • Removed note about unsupported NativeLink gate level simulation.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Corrected load design syntax error.
2016.05.02 16.0.0
  • Removed support for NativeLink simulation in Pro Edition
  • Added note about avoiding ModelSim - Intel FPGA Edition instance limitations.
2015.11.02 15.1.0 Changed instances of Quartus II to Quartus Prime.

2015.05.04

15.0.0
  • Added mixed language simulation support in the ModelSim - Intel FPGA Edition software.

2014.06.30

14.0.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.

November 2012

12.1.0

  • Relocated general simulation information to Simulating Altera Designs.

June 2012

12.0.0

  • Removed survey link.

November 2011

11.0.1

  • Changed to new document template.
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