Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

Download PDF
ID 683870
Date 4/13/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
2.1. Supported Simulators 2.2. Supported Simulation Levels 2.3. Supported Hardware Description Languages 2.4. Supported Simulation Flows 2.5. Preparing for Simulation 2.6. Running a Simulation (Custom Flow) 2.7. Intel FPGA Simulation Basics Revision History
2.5. Preparing for Simulation x
2.5.1. Compiling Simulation Model Libraries 2.5.2. Using The EDA Netlist Writer 2.5.3. Simulating Intel® FPGA IP Cores
2.5.3. Simulating Intel® FPGA IP Cores x
2.5.3.1. Generating IP Simulation Files 2.5.3.2. Scripting IP Simulation
2.5.3.2. Scripting IP Simulation x
2.5.3.2.1. Generating a Combined Simulator Setup Script 2.5.3.2.2. Incorporating Simulator Setup Scripts from the Generated Template
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support x
3.1. Quick Start Example (ModelSim with Verilog) 3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines 3.3. ModelSim Simulation Setup Script Example 3.4. Sourcing ModelSim* or QuestaSim Simulator Setup Scripts 3.5. Unsupported Features 3.6. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support Revision History
3.2. Questa* Intel® FPGA Edition, ModelSim, and QuestaSim Simulator Guidelines x
3.2.1. Using Questa* Intel® FPGA Edition Precompiled Libraries 3.2.2. Passing Parameter Information from Verilog HDL to VHDL 3.2.3. Viewing Simulation Messages 3.2.4. Generating Signal Activity Data for Power Analysis 3.2.5. Viewing Simulation Waveforms 3.2.6. Simulating with Questa* Intel® FPGA Edition Waveform Editor
3.2.4. Generating Signal Activity Data for Power Analysis x
3.2.4.1. Generating Standard Delay Output for Power Analysis
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa* Intel® FPGA Edition, ModelSim* , and QuestaSim* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

5. Aldec Active-HDL and Riviera-PRO Support

You can include your supported EDA simulator in the design flow. This chapter provides specific guidelines for simulation of designs with the Aldec Active-HDL or Riviera-PRO software.

Section Content
Quick Start Example (Active-HDL VHDL)
Aldec Active-HDL and Riviera-PRO Guidelines
Using Simulation Setup Scripts
Sourcing Aldec ActiveHDL or Riviera Pro Simulator Setup Scripts
Aldec Active-HDL and Riviera-PRO Support Revision History

Level Two Title