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1.1. Features
1.2. IP Core Device Support
1.3. Resource Utilization and Performance
1.4. Functional Description
1.5. Parameter Settings
1.6. Installing and Licensing Intel® FPGA IP Cores
1.7. Customizing and Generating IP Cores
1.8. Document Revision History for Error Message Register Unloader Intel® FPGA IP IP Core User Guide
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1.4.1. Error Message Register
Some single event upset (SEU) FPGA devices contain built-in error detection circuitry to detect a flip in any of the device's CRAM bits due to a soft error.
The bit assignments for the device EMR vary by device family. For details on the EMR bits for your FPGA device family, refer to the device handbook’s SEU mitigation chapter.