Intel Cyclone 10 LP Device Design Guidelines

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ID 683861
Date 3/28/2019
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Design Guidelines
Intel® Cyclone® 10 LP Device Design Guidelines x
Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Device Variant PLLs and Clock Routing Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering Speed Grade Vertical Device Migration
Early System and Board Planning x
Early Power Estimation Planning for Device Configuration Planning for On-chip Debugging
Planning for Device Configuration x
Configuration Scheme Selection Configuration Features Intel® Quartus® Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables
Intel® Quartus® Prime Configuration Settings x
Optional Configuration Pins
Planning for On-chip Debugging x
On-chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-related Intel® Quartus® Prime Settings Signal Integrity Considerations Board-level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL Board Design Guidelines
Configuration Pin Connections x
Clock Trace Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
JTAG Pins x
JTAG Pin Connections Download Cable Operating Voltage JTAG Signal Buffering
Board-related Intel® Quartus® Prime Settings x
Device-wide Output Enable Pin Unused Pins
Signal Integrity Considerations x
Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Features I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable Standards and Flexible I/O Banks Dual-Purpose and Special Pin Connections Intel® Cyclone® 10 LP I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Recommended HDL Coding Styles Register Power-up Levels and Control Signals
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Intel® Quartus® Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Simulation Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Intel® Quartus® Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Clock Power Management Memory Power Reduction I/O Power Guidelines
Intel® Cyclone® 10 LP Device Design Guidelines

Selectable Standards and Flexible I/O Banks

Table 43.  Selectable Standards and Flexible I/O Banks Checklist
Number Done? Checklist Item
1   Select a suitable signaling type and I/O standard for each I/O pin.
2   Ensure that the appropriate I/O standard support is supported in the targeted I/O bank.
3   Place I/O pins that share voltage levels in the same I/O bank.
4   Verify that all output signals in each I/O bank are intended to drive out at the bank’s VCCIO voltage level.
5   Verify that all voltage-referenced signals in each I/O bank are intended to use the bank’s VREF voltage level.
6   Check the I/O bank support for LVDS features. Different I/O banks include different support for LVDS signaling.

Intel® Cyclone® 10 LP devices have eight I/O banks. All differential I/O standards are supported in all banks. The only exception is HSTL-12 Class II, which is only supported in column I/O banks.

You can assign I/O standards and make other I/O-related settings in the Pin Planner.

The board must supply each bank with one VCCIO voltage level for every VCCIO pin in the bank. Each I/O bank is powered by the VCCIO pins of that particular bank and is independent of the VCCIO power supply of other I/O banks. A single I/O bank supports output signals that are driving at the same voltage as the VCCIO power supply. An I/O bank can simultaneously support any number of input signals with different I/O standards, with some exceptions for voltage-referenced inputs. Voltage-referenced standards are supported in an I/O bank using any number of single-ended or differential standards, as long as they use the same VREF and VCCIO values.

When you use the VREF pins as regular I/Os, they have higher pin capacitance than regular user I/O pins. This has an impact on the timing if the pins are used as inputs and outputs.

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