Intel Cyclone 10 LP Device Design Guidelines

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ID 683861
Date 3/28/2019
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Design Guidelines
Intel® Cyclone® 10 LP Device Design Guidelines x
Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Device Variant PLLs and Clock Routing Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering Speed Grade Vertical Device Migration
Early System and Board Planning x
Early Power Estimation Planning for Device Configuration Planning for On-chip Debugging
Planning for Device Configuration x
Configuration Scheme Selection Configuration Features Intel® Quartus® Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables
Intel® Quartus® Prime Configuration Settings x
Optional Configuration Pins
Planning for On-chip Debugging x
On-chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-related Intel® Quartus® Prime Settings Signal Integrity Considerations Board-level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL Board Design Guidelines
Configuration Pin Connections x
Clock Trace Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
JTAG Pins x
JTAG Pin Connections Download Cable Operating Voltage JTAG Signal Buffering
Board-related Intel® Quartus® Prime Settings x
Device-wide Output Enable Pin Unused Pins
Signal Integrity Considerations x
Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Features I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable Standards and Flexible I/O Banks Dual-Purpose and Special Pin Connections Intel® Cyclone® 10 LP I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Recommended HDL Coding Styles Register Power-up Levels and Control Signals
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Intel® Quartus® Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Simulation Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Intel® Quartus® Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Clock Power Management Memory Power Reduction I/O Power Guidelines
Intel® Cyclone® 10 LP Device Design Guidelines

Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines

Document Version Changes
2019.03.28 Removed the information about on-die decoupling capacitors from the Decoupling Capacitors section. Intel® Cyclone® 10 LP devices do not have on-die decoupling capacitors.
2019.01.25
  • Rebranded as Intel.
  • Updated the following terms:
    • Changed Qsys to Platform Designer
    • Changed OpenCore Plus to Intel FPGA IP Evaluation Mode
    • Changed TimeQuest Timing Analyzer to Timing Analyzer
  • Removed the information about power sequencing from the Device Power-up section. Power sequencing is not applicable for Intel® Cyclone® 10 LP devices.
  • Added conditions to use VCCIO or VCCA when powering JTAG pins in Intel® Cyclone® 10 LP devices in the Download Cable Operating Voltage section.
  • Removed information about the BluePrint Platform Designer feature in the Making FPGA Pin Assignments section. This feature is no longer supported in the Intel® Quartus® Prime Standard Edition software.
  • Removed information about the Early Timing Estimation feature from the Area and Timing Optimization section. This feature is no longer supported in the Intel® Quartus® Prime Standard Edition software.
Date Version Changes
May 2017 2017.05.08 Initial release.

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