AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
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Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge

The final components you'll need to add and configure are an On-Chip RAM, a JTAG UART, and an Avalon-MM Pipeline Bridge.
  1. Type ram in the IP Catalog search box and double-click On-Chip Memory (RAM or ROM).
  2. In the On-Chip Memory (RAM or ROM) parameter editor, in the Size box, set the Total memory size to 8192 bytes.
  3. To add the On-Chip Memory (RAM or ROM) component to your design, click Finish.
  4. Right-click the name of the On-Chip Memory (RAM or ROM) component and click Rename. Type onchip_ram to change the name.
  5. Type jtag uart in the IP Catalog search box and double-click JTAG UART.
  6. To add the JTAG UART component to your design with default settings, click Finish.
  7. Right-click the name of the JTAG UART component and click Rename. Type jtag_uart to change the name.
  8. Type pipeline bridge in the IP Catalog search box and double-click Avalon-MM Pipeline Bridge.
  9. In the Avalon-MM Pipeline Bridge parameter editor, change the following settings:
    • Set the Address width to 16.
    • Set the Maximum pending read transactions to 1.
  10. To add the Avalon-MM Pipeline Bridge to your design, click Finish.
  11. Right-click the name of the Avalon-MM Pipeline Bridge component and click Rename. Type pipeline_bridge to change the name.
  12. In the Export column, double-click the entry that corresponds to the m0 signal for the pipeline_bridge component and type master.

The Avalon-MM Pipeline Bridge allows the processor subsystem cpu_subsystem to export a single Avalon-MM master interface. Your design can then access the slave interfaces in a higher-level system, and handle address offsets automatically. The bridge also improves timing performance.

All the required components are now included in this subsystem. Compare the settings in your design with the following figure and make sure your components and exported interfaces are named correctly.

Figure 10. Export Names for cpu_subsystem Components
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