Altera provides an design example with the HMC Controller IP core. The design example is available both for simulation of your IP core and for compilation. The design example in simulation functions as the HMC Controller IP core testbench.

If you click Generate Example Design in the HMC Controller parameter editor, the Quartus® Prime software generates a demonstration testbench. The parameter editor prompts you for the desired location of the testbench.

To simulate the testbench, you must provide your own HMC bus functional model (BFM). Altera tests the design example testbench with the Micron Hybrid Memory Cube BFM. The testbench does not include an I²C master module, because the Micron HMC BFM does not support and does not require configuration by an I²C module.

In simulation, the testbench controls a TX PLL and the data path interfaces to perform the following sequence of actions:

1. Configures the HMC BFM with the HMC Controller IP core data rate and channel width, in Response Open Loop Mode.
2. Establishes the link between the BFM and the IP core.
3. Directs each of the IP core's four ports to write four packets of data to the BFM.
4. Directs the IP core to read back the data from the BFM.
5. Checks that the read data matches the write data.
6. If the data matches, displays TEST_PASSED.