Hybrid Memory Cube Controller Design Example User Guide

ID 683817
Date 5/02/2016
Public

2.5. Interface Signals

Table 3.  HMC Controller IP Core Design Example Signals
Signal Name Direction Width (Bits) Description
clk_50 Input 1 50 MHz input clock.
hssi_refclk Input 1 CDR reference clock for HMC and HMCC IP core.
hmc_lxrx Input Channel Count (16 or 8) FPGA transceiver receive pins.
hmc_lxtx Output Channel Count (16 or 8) FPGA transceiver transmit pins.
hmc_ctrl_lxrxps Input 1 FPGA transceiver power save control.
hmc_ctrl_lxtxps Output 1 HMC transceiver power save control.
hmc_ctrl_ferr_n Input 1 HMC FERR_N output.
hmc_ctrl_p_rst_n Output 1 HMC P_RST_N input.
hmc_ctrl_scl Bi-Directional 1 HMC I2C configuration clock.
hmc_ctrl_sda Bi-Directional 1 HMC I2C configuration data.
fmc0_scl Output 1 Unused. Driven low to protect the FPGA I/O pins from the 3.3 V pullup on the daughter card.
fmc0_sda Output 1 Unused. Driven low to protect the FPGA I/O pins from the 3.3 V pullup on the daughter card.
push_button Input 1 Push button input used for reset.
heart_beat_n Output 1 Heartbeat LED output.
link_init_complete_n Output 1 Link initialization complete LED output.
test_passed_n Output 1 Test passed LED output.
test_failed_n Output 1 Test failed LED output.