Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683809
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture 3. Developing Your Intel® Stratix® 10 Custom Platform 4. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Introduction to Intel® Reference Platform 1.2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform 1.4. Contents of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform
1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform x
1.3.1. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Board Variants
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture x
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® 2.2. DDR4 as Global Memory for OpenCL Applications 2.3. Host Connection to OpenCL Kernels 2.4. Partial Reconfiguration 2.5. Other Components in the Reference Design 2.6. Intel® Stratix® 10 FPGA System Design 2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows 2.9. Addition of Timing Constraints 2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.11. Intel® Stratix® 10 FPGA Programming Flow 2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® x
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access 2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP 2.1.3. Instantiation of the version_id Component 2.1.4. Board Support Package Software Layer 2.1.5. Direct Memory Access 2.1.6. Message Signaled Interrupt 2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
2.1.4. Board Support Package Software Layer x
2.1.4.1. Common Hardware Constants in Software Headers Files 2.1.4.2. PCIe Kernel Driver 2.1.4.3. Host-to-Device MMD Software Implementation
2.1.5. Direct Memory Access x
2.1.5.1. Implementing a DMA Transfer
2.2. DDR4 as Global Memory for OpenCL Applications x
2.2.1. DDR4 IP Instantiation 2.2.2. DDR4 Connection to PCIe Host 2.2.3. DDR4 Connection to the OpenCL Kernel
2.4. Partial Reconfiguration x
2.4.1. Constant Address Bridge (constant_address_bridge)
2.6. Intel® Stratix® 10 FPGA System Design x
2.6.1. Clocks 2.6.2. Resets 2.6.3. Floorplan 2.6.4. Global Routing 2.6.5. Pipelining 2.6.6. DDR4 Calibration
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design x
2.7.1. Supply the Kernel Clock 2.7.2. Guarantee Kernel Clock Timing 2.7.3. Provide a Timing-Closed Post-Fit Netlist
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows x
2.8.1. Compile Flow 2.8.2. Platform Designer System Generation 2.8.3. QAR/QDB File Generation
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ x
2.10.1. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.10.2. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
2.12.1. aocl install 2.12.2. aocl uninstall 2.12.3. aocl program 2.12.4. aocl flash 2.12.5. aocl diagnose 2.12.6. aocl list-devices
3. Developing Your Intel® Stratix® 10 Custom Platform x
3.1. Initializing Your Intel® Stratix® 10 Custom Platform 3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment 3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication 3.6. Branding Your Intel® Stratix® 10 Custom Platform 3.7. Changing the Device Part Number 3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform 3.9. Modifying the Kernel PLL Reference Clock 3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform 3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture
3. Developing Your Intel® Stratix® 10 Custom Platform
4. Document Revision History

1.1. Introduction to Intel® Reference Platform

The Intel® FPGA SDK for OpenCL™ provides you an environment to target FPGAs while abstracting FPGA details.

It allows you to target Intel® FPGA devices either on reference platforms provided by Intel® or Intel® board partners, or on your own custom platforms. A typical setup for using the SDK is illustrated in the following image:

Figure 1. Setup for Using Intel® FPGA SDK for OpenCL™

The setup consists of a host application running on the host processor and offloading kernel tasks to the FPGA. The OpenCL kernel is converted to a hardware circuit by the SDK compiler. Leveraging this capability for your FPGA platform requires an Intel® FPGA SDK for OpenCL™ -compatible Board Support Package (BSP). The BSP describes the reference platform to the SDK.

The following illustration depicts segments of the Intel® FPGA SDK for OpenCL™ solution:

Figure 2. Layers of Intel® FPGA SDK for OpenCL™

Your host application communicates with the BSP layers through the Hardware Abstraction Layer (HAL). A typical Intel® BSP consists of software layers and a hardware project created using the Intel® Quartus® Prime Pro Edition software. The hardware project consists of FPGA board peripheral IPs and custom IPs.

The following illustration depicts the hardware project components, and how these components communicate with software layers:

Figure 3.  Intel® FPGA SDK for OpenCL™ Complete Solution

In Intel® FPGA SDK for OpenCL™ Complete Solution, left side depicts the host application running on host processor while right side depicts the FPGA hardware acceleration board. If you are developing a custom platform to run your software applications, then you must create a custom BSP for your platform. In that case, everything that appears in blue in the image must be included in your custom BSP as follows:

  • On the FPGA side, your custom BSP must include all hardware necessary to communicate with the host and the memory, that is, DDR and/or QDR memory interfaces, the DMA host interface (which can be PCIe), and any streaming interfaces to be implemented as channels. The Intel® FPGA SDK for OpenCL™ compiles your OpenCL kernel into a data flow circuit, connects to the BSP hardware components, and generates an FPGA image for this combined circuit, which is used to configure the FPGA.
  • On the host side, your custom BSP must provide the Memory Mapped Device layer (MMD) (in the form of a library) to facilitate communication between OpenCL libraries and your hardware. When you compile your host application, the host application links with both the Intel® FPGA SDK for OpenCL™ and MMD libraries to form a host executable.

Intel® provides reference BSPs for Intel® FPGA development kits. Most of these reference BSPs are included in the installed directory for Intel® FPGA SDK for OpenCL™ :

Table 1.   Reference BSPs for Intel® FPGA development kits
Reference BSP Install Path
Intel® Arria® 10 GX FPGA Reference Platform Installed with the Intel® FPGA SDK for OpenCL™ in INTELFPGAOCLSDKROOT/board/a10_ref.
Intel® Stratix® 10 GX FPGA Reference Platform Installed with the Intel® FPGA SDK for OpenCL™ in INTELFPGAOCLSDKROOT/board/s10_ref.
Intel® Arria® 10 SoC FPGA Reference Platform Installed with the Intel® FPGA SDK for OpenCL™ in INTELFPGAOCLSDKROOT/board/a10soc.
Attention: Cyclone® V SoC and Stratix® V GX reference platforms are also available within the Intel® FPGA SDK for OpenCL™ installation of version 18.0 and earlier.

You can use one of the above BSPs as a reference to get started with custom BSP development. You can also use reference platforms from one of the following Intel® FPGA’s preferred board partners and download BSP from their website if it matches your hardware requirements:

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